component
AD7367BRUZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ad7367bruz-rl7",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"adc-dac-data conversion",
"ad7367bruz-rl7",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ad7367bruz-rl7.kicad_sym",
"ad7367bruz-rl7.kicad_mod",
"ad7367bruz-rl7.glb",
"ad7367bruz-rl7.step",
"ad7367bruz-rl7.lbr",
"docs/hero.png",
"docs/ad7367bruz-rl7-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ad7367bruz-rl7-hero.glb",
"ad7367bruz-rl7-hero.overlay.json",
"ad7367bruz-rl7-etched.glb"
],
"component": {
"mpn": "AD7367BRUZ-RL7",
"manufacturer": "Analog Devices",
"package": "TSSOP-24",
"pin_count": 24,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7366_7367.pdf",
"parts": {
"symbol": "ad7367bruz-rl7.kicad_sym",
"footprint": "ad7367bruz-rl7.kicad_mod",
"model_3d": "ad7367bruz-rl7-hero.glb",
"model_3d_plain": "ad7367bruz-rl7-etched.glb",
"model_3d_step": "ad7367bruz-rl7-etched.step",
"model_3d_step_plain": "ad7367bruz-rl7.step",
"lbr": "ad7367bruz-rl7.lbr"
},
"distributor_links": {
"lcsc": "C650863",
"digikey": "AD7367BRUZ-RL7TR-ND",
"mouser": "584-AD7367BRUZ-R7"
},
"distributor_check": {
"checked_at": "2026-10-28T20:15:04Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "AD7367BRUZ-RL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD7367BRUZ-R7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "DOUTA",
"type": "output",
"description": "Serial data output for ADC A; bits are clocked out on the falling edge of SCLK, with 12 SCLK cycles for the AD7366 and 14 for the AD7367, MSB first."
},
{
"number": "2",
"name": "VDRIVE",
"type": "power_in",
"description": "Logic power supply input that sets the interface voltage; it must be 2.7 V to 5.25 V, must not exceed DVCC or AVCC by more than 0.3 V, and must be at least 4.75 V to reach 1.12 MSPS (AD7366) or 1 MSPS (AD7367)."
},
{
"number": "3",
"name": "DVCC",
"type": "power_in",
"description": "Digital supply voltage of 4.75 V to 5.25 V that should be decoupled to DGND with 10 µF and 100 nF capacitors and ideally shorted to AVCC."
},
{
"number": "4",
"name": "RANGE1",
"type": "input",
"description": "Logic input that, together with RANGE0, selects the analog input range (±10 V, ±5 V or 0 V to 10 V, or ±12 V with an external 3 V reference)."
},
{
"number": "5",
"name": "RANGE0",
"type": "input",
"description": "Logic input that, together with RANGE1, selects the analog input range as described in Table 8 of the datasheet."
},
{
"number": "6",
"name": "ADDR",
"type": "input",
"description": "Multiplexer select logic input that chooses Channel 1 or Channel 2 of both ADCs, latched on the rising edge of BUSY."
},
{
"number": "7",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry and external references; it must be no more than 0.3 V from DGND, even on a transient basis."
},
{
"number": "8",
"name": "AVCC",
"type": "power_in",
"description": "Analog supply voltage of 4.75 V to 5.25 V for the ADC cores, decoupled to AGND with 10 µF and 100 nF capacitors."
},
{
"number": "9",
"name": "DCAPA",
"type": "passive",
"description": "Decoupling pin for the ADC A reference buffer, where 680 nF is recommended; an external reference can be applied here when REFSEL is low."
},
{
"number": "10",
"name": "VSS",
"type": "power_in",
"description": "Negative high-voltage supply for the analog input structure, which must be less than −11.5 V for all input ranges and is decoupled with 10 µF and 100 nF capacitors."
},
{
"number": "11",
"name": "VA1",
"type": "input",
"description": "Single-ended analog input channel 1 of ADC A, with its input range set by RANGE0 and RANGE1."
},
{
"number": "12",
"name": "VA2",
"type": "input",
"description": "Single-ended analog input channel 2 of ADC A, with its input range set by RANGE0 and RANGE1."
},
{
"number": "13",
"name": "VB2",
"type": "input",
"description": "Single-ended analog input channel 2 of ADC B, with its input range set by RANGE0 and RANGE1."
},
{
"number": "14",
"name": "VB1",
"type": "input",
"description": "Single-ended analog input channel 1 of ADC B, with its input range set by RANGE0 and RANGE1."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "Positive high-voltage supply for the analog input structure, which must be greater than 11.5 V for all input ranges and is decoupled with 10 µF and 100 nF capacitors."
},
{
"number": "16",
"name": "DCAPB",
"type": "passive",
"description": "Decoupling pin for the ADC B reference buffer, where 680 nF is recommended; an external reference can be applied here when REFSEL is low."
},
{
"number": "17",
"name": "AGND",
"type": "power_in",
"description": "Second analog ground pin, to be connected to the system AGND plane."
},
{
"number": "18",
"name": "REFSEL",
"type": "input",
"description": "Internal/external reference select; logic high selects the on-chip 2.5 V reference (with DCAPA and DCAPB tied to decoupling capacitors), and logic low allows an external reference via DCAPA and/or DCAPB."
},
{
"number": "19",
"name": "CS",
"type": "input",
"description": "Active-low chip select that frames the serial transfer and enables the output bus so results appear on DOUTA and DOUTB."
},
{
"number": "20",
"name": "SCLK",
"type": "input",
"description": "Serial clock logic input that provides the clock for accessing conversion data."
},
{
"number": "21",
"name": "CNVST",
"type": "input",
"description": "Edge-triggered conversion start; its falling edge puts the track/hold into hold and starts conversion, and holding it low at the end of a conversion powers the part down until its rising edge."
},
{
"number": "22",
"name": "BUSY",
"type": "output",
"description": "Busy output that goes high when a conversion starts and stays high until the conversion is complete."
},
{
"number": "23",
"name": "DOUTB",
"type": "output",
"description": "Serial data output for ADC B with the same clocking as DOUTA; data from both ADCs can also be read sequentially on either DOUT pin when CS is held low for a further 14 SCLK cycles."
},
{
"number": "24",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference for all digital circuitry, to be connected to the system DGND plane and kept within 0.3 V of AGND."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Table 6 assigns RANGE1=4, RANGE0=5, ADDR=6, but the garbled Figure 2 text on page 9 shows ADDR at 4 ; Table 6 lists pins 1 and 23 as DOUTA and DOUTB without explicit order. DOUTA=1 and DOUTB=23 were inf; Table 6 lists VB2 before VB1 for pins 13 and 14, so VB2=13 and VB1=14 were taken as written; confirm"
],
"pages_sent": 8,
"cost_usd": 0.0737,
"at": "2026-10-28T20:14:51"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7366_7367.pdf",
"pages": 28,
"sha256": "73011d26fda7310e",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 24,
"described": 24,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad7367bruz-rl7.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
7.8,
0.97
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",
"checked": "2026-10-28",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad7367bruz-rl7-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
7.8,
0.97
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "90fb51c63a6cde71a30a22af40ac16d80f2048d2539dcd9f2c47a2001e2cf622",
"checked": "2026-10-28",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "RU-24",
"source_page": 28,
"D": {
"nom_mm": 7.8,
"range_mm": [
7.7,
7.9
]
},
"E1": {
"nom_mm": 4.4,
"range_mm": [
4.3,
4.5
]
},
"E": {
"nom_mm": 6.4,
"range_mm": [
null,
null
]
},
"e": {
"nom_mm": 0.65,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.2,
"range_mm": [
null,
1.2
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ad7367bruz-rl7.step",
"verdict": "PASS",
"reasons": [
"height and body within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}