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AD7367BRUZ-RL7

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Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7367BRUZ-RL7

Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24

AD7367BRUZ-RL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DOUTA output Serial data output for ADC A; bits are clocked out on the falling edge of SCLK, with 12 SCLK cycles for the AD7366 and 14 for the AD7367, MSB first.
2 VDRIVE power_in Logic power supply input that sets the interface voltage; it must be 2.7 V to 5.25 V, must not exceed DVCC or AVCC by more than 0.3 V, and must be at least 4.75 V to reach 1.12 MSPS (AD7366) or 1 MSPS (AD7367).
3 DVCC power_in Digital supply voltage of 4.75 V to 5.25 V that should be decoupled to DGND with 10 µF and 100 nF capacitors and ideally shorted to AVCC.
4 RANGE1 input Logic input that, together with RANGE0, selects the analog input range (±10 V, ±5 V or 0 V to 10 V, or ±12 V with an external 3 V reference).
5 RANGE0 input Logic input that, together with RANGE1, selects the analog input range as described in Table 8 of the datasheet.
6 ADDR input Multiplexer select logic input that chooses Channel 1 or Channel 2 of both ADCs, latched on the rising edge of BUSY.
7 AGND power_in Analog ground reference for all analog circuitry and external references; it must be no more than 0.3 V from DGND, even on a transient basis.
8 AVCC power_in Analog supply voltage of 4.75 V to 5.25 V for the ADC cores, decoupled to AGND with 10 µF and 100 nF capacitors.
9 DCAPA passive Decoupling pin for the ADC A reference buffer, where 680 nF is recommended; an external reference can be applied here when REFSEL is low.
10 VSS power_in Negative high-voltage supply for the analog input structure, which must be less than −11.5 V for all input ranges and is decoupled with 10 µF and 100 nF capacitors.
11 VA1 input Single-ended analog input channel 1 of ADC A, with its input range set by RANGE0 and RANGE1.
12 VA2 input Single-ended analog input channel 2 of ADC A, with its input range set by RANGE0 and RANGE1.
13 VB2 input Single-ended analog input channel 2 of ADC B, with its input range set by RANGE0 and RANGE1.
14 VB1 input Single-ended analog input channel 1 of ADC B, with its input range set by RANGE0 and RANGE1.
15 VDD power_in Positive high-voltage supply for the analog input structure, which must be greater than 11.5 V for all input ranges and is decoupled with 10 µF and 100 nF capacitors.
16 DCAPB passive Decoupling pin for the ADC B reference buffer, where 680 nF is recommended; an external reference can be applied here when REFSEL is low.
17 AGND power_in Second analog ground pin, to be connected to the system AGND plane.
18 REFSEL input Internal/external reference select; logic high selects the on-chip 2.5 V reference (with DCAPA and DCAPB tied to decoupling capacitors), and logic low allows an external reference via DCAPA and/or DCAPB.
19 CS input Active-low chip select that frames the serial transfer and enables the output bus so results appear on DOUTA and DOUTB.
20 SCLK input Serial clock logic input that provides the clock for accessing conversion data.
21 CNVST input Edge-triggered conversion start; its falling edge puts the track/hold into hold and starts conversion, and holding it low at the end of a conversion powers the part down until its rising edge.
22 BUSY output Busy output that goes high when a conversion starts and stays high until the conversion is complete.
23 DOUTB output Serial data output for ADC B with the same clocking as DOUTA; data from both ADCs can also be read sequentially on either DOUT pin when CS is held low for a further 14 SCLK cycles.
24 DGND power_in Digital ground reference for all digital circuitry, to be connected to the system DGND plane and kept within 0.3 V of AGND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-24
Category ADC/DAC/Data Conversion
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-Noise Ratio (SNR) SNR 74 76 dB fIN = 50 kHz sine wave 5
Signal-to-Noise + Distortion Ratio (SINAD) SINAD 73 75 dB fIN = 50 kHz sine wave 5
Total Harmonic Distortion (THD) THD -84 -78 dB fIN = 50 kHz sine wave 5
Spurious-Free Dynamic Range (SFDR) SFDR -87 -79 dB fIN = 50 kHz sine wave 5
Integral Nonlinearity (INL) INL -3.5 2 3.5 LSB 5
Differential Nonlinearity (DNL) DNL -0.9 0.5 0.9 LSB Guaranteed no missed codes to 14 bits 5
Positive Full-Scale Error -20 4 20 LSB ±5 V and ±10 V analog input range 5
Positive Full-Scale Error -20 5 20 LSB 0 V to 10 V analog input range 5
Positive Full-Scale Error Match -3 3 LSB Matching from ADC A to ADC B 5
Positive Full-Scale Error Match (channel-to-channel) -0.2 0.2 LSB Channel-to-channel matching for ADC A and ADC B 5
Zero Code Error -10 1 10 LSB ±5 V and ±10 V analog input range 5
Zero Code Error -20 5 20 LSB 0 V to 10 V analog input range 5
Zero Code Error Match -3 3 LSB Matching from ADC A to ADC B 5
Zero Code Error Match (channel-to-channel) -0.2 0.2 LSB Channel-to-channel matching for ADC A and ADC B 5
Negative Full-Scale Error -20 4 20 LSB ±5 V and ±10 V analog input range 5
Negative Full-Scale Error -20 5 20 LSB 0 V to 10 V analog input range 5
Negative Full-Scale Error Match -3 3 LSB Matching from ADC A to ADC B 5
Negative Full-Scale Error Match (channel-to-channel) -0.2 0.2 LSB Channel-to-channel matching for ADC A and ADC B 5
Reference Output Voltage VREF 2.495 2.5 2.505 V ±0.2% max @ 25°C 6
Reference Input Voltage Range VREF 2.5 3 V 6
DC Leakage Current (external reference applied) -1 0.01 1 µA External reference applied to Pin DCAPA/Pin DCAPB 6
Reference Temperature Coefficient 25 ppm/°C 6
Input Current IIN -1 0.01 1 µA VIN = 0 V or VDRIVE 6
Input Low Voltage VINL 0.8 V 6
Output Low Voltage VOL 0.4 V 6
VCC (AVCC/DVCC supply) VCC 4.75 5.25 V See Table 7 6
VDD (positive high-voltage supply) VDD 11.5 16.5 V See Table 7 6
VSS (negative high-voltage supply) VSS -16.5 -11.5 V See Table 7 6
VDRIVE (logic supply) VDRIVE 2.7 5.25 V 6
IDD Normal Mode (Static) IDD 370 550 µA Normal Mode (Static), VDD = +16.5 V 6
ISS Normal Mode (Static) ISS 40 60 µA Normal Mode (Static), VSS = −16.5 V 6
ICC Normal Mode (Static) ICC 1.5 2.25 mA Normal Mode (Static), VCC = 5.5 V 6
IDD Normal Mode (Operational) IDD 1.8 2 mA fS = 1 MSPS, VDD = +16.5 V 6
ISS Normal Mode (Operational) ISS 1.5 1.6 mA fS = 1 MSPS, VSS = −16.5 V 6
ICC Normal Mode (Operational) ICC 5 5.65 mA fS = 1 MSPS, VCC = 5.25 V, internal reference enabled 6
IDD Shutdown Mode IDD 0.01 1 µA Shutdown Mode, VDD = +16.5 V 6
ISS Shutdown Mode ISS 0.01 1 µA Shutdown Mode, VSS = −16.5 V 6
ICC Shutdown Mode ICC 0.3 3 µA Shutdown Mode, VCC = 5.25 V 6
Power Dissipation Normal Mode (Operational) 80.7 89.1 mW VDD = +16.5 V, VSS = −16.5 V, VCC = 5.25 V 6
Conversion time (AD7367) tCONVERT 680 ns CNVST falling edge to BUSY falling edge; 2.7 V ≤ VDRIVE < 4.75 V 7
Serial read clock frequency fSCLK 10 kHz Minimum, both VDRIVE ranges 7
Serial read clock frequency fSCLK 35 MHz 2.7 V ≤ VDRIVE < 4.75 V 7
Serial read clock frequency fSCLK 48 MHz 4.75 V ≤ VDRIVE ≤ 5.25 V 7
Data access time after SCLK falling edge (t5) t5 20 ns 2.7 V ≤ VDRIVE < 4.75 V; output crosses 0.4 V or 2.4 V 7
Data access time after SCLK falling edge (t5) t5 14 ns 4.75 V ≤ VDRIVE ≤ 5.25 V; output crosses 0.4 V or 2.4 V 7
SCLK to data valid hold time (t6) t6 7 ns 7
Power-up time from shutdown (tPOWER-UP) tPOWER-UP 70 µs Time between CNVST rising edge and CNVST falling edge 7
VDD to AGND, DGND VDD -0.3 16.5 V 8
VSS to AGND, DGND VSS -16.5 0.3 V 8
VDRIVE to DGND VDRIVE -0.3 V Upper limit printed as DVCC (not numeric) 8
AVCC to AGND, DGND AVCC -0.3 7 V 8
DVCC to AVCC -0.3 0.3 V 8
DVCC to DGND DVCC -0.3 7 V 8
Input Current to Any Pin Except Supplies -10 10 mA Except supplies; transients up to 100 mA do not cause latch-up 8
Operating Temperature Range TA -40 85 °C 8
Storage Temperature Range -65 150 °C 8
Junction Temperature TJ 150 °C 8
θJA Thermal Impedance θJA 128 °C/W TSSOP package 8
θJC Thermal Impedance θJC 42 °C/W TSSOP package 8

CAD (KiCad official)

  • Symbol: AD7367BRUZ-RL7
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ad7367bruz-rl7-etched.step / ad7367bruz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7367bruz-rl7.step / ad7367bruz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 73011d26fda7310e, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF