component
AD7356BRUZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7356BRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-16
AD7356BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VINA+ | input | Non-inverting analog input of ADC A, forming a fully differential pair with VINA−. |
| 2 | VINA− | input | Inverting analog input of ADC A, forming a fully differential pair with VINA+. |
| 3 | REFA | bidirectional | Reference decoupling pin for ADC A (10 µF recommended to REFGND); carries the nominal 2.048 V internal reference and can be overdriven by an external reference of 2.048 V + 100 mV to VDD. |
| 4 | REFGND | power_in | Reference ground for the reference circuitry; connect to the system AGND plane, with decoupling capacitors placed between this pin and REFA/REFB. |
| 5 | AGND | power_in | Analog ground reference for all analog circuitry; AGND and DGND must not differ by more than 0.3 V, even transiently. |
| 6 | REFB | bidirectional | Reference decoupling pin for ADC B (10 µF recommended to REFGND); carries the nominal 2.048 V internal reference and can be overdriven by an external reference of 2.048 V + 100 mV to VDD. |
| 7 | VINB− | input | Inverting analog input of ADC B, forming a fully differential pair with VINB+. |
| 8 | VINB+ | input | Non-inverting analog input of ADC B, forming a fully differential pair with VINB−. |
| 9 | VDD | power_in | Power supply input, 2.5 V ± 10%, decoupled to AGND with 0.1 µF in parallel with 10 µF tantalum. |
| 10 | CS | input | Active-low chip select that initiates conversions and frames the serial data transfer. |
| 11 | AGND | power_in | Analog ground reference for all analog circuitry; AGND and DGND must not differ by more than 0.3 V, even transiently. |
| 12 | DGND | power_in | Digital ground reference for all digital circuitry; connect to the system DGND plane and keep within 0.3 V of AGND. |
| 13 | SDATAB | output | Serial data output for ADC B, MSB first, clocked out on SCLK falling edges (14 SCLK falling edges for 12 data bits after two leading zeros). |
| 14 | SDATAA | output | Serial data output for ADC A, MSB first, clocked out on SCLK falling edges (14 SCLK falling edges for 12 data bits after two leading zeros). |
| 15 | SCLK | input | Serial clock logic input for accessing data and also the clock source for the conversion process. |
| 16 | VDRIVE | power_in | Logic power supply input setting the interface voltage (2.25 V to 3.6 V per specifications), decoupled to DGND with 0.1 µF in parallel with 10 µF tantalum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD | VDD | 2.25 | 2.75 | V | Nominal VDD = 2.5 V | 4 | |
| Logic supply VDRIVE | VDRIVE | 2.25 | 3.6 | V | 4 | ||
| Signal-to-Noise Ratio | SNR | 70 | 71.5 | dB | fIN = 1 MHz sine wave | 3 | |
| Signal-to-(Noise and Distortion) | SINAD | 69.5 | 71 | dB | fIN = 1 MHz sine wave | 3 | |
| Total Harmonic Distortion | THD | -84 | -77.5 | dB | fIN = 1 MHz sine wave | 3 | |
| Spurious Free Dynamic Range | SFDR | -85 | -78.5 | dB | fIN = 1 MHz sine wave | 3 | |
| Integral Nonlinearity | INL | 0.5 | 1 | LSB | printed ± | 3 | |
| Differential Nonlinearity | DNL | 0.5 | 0.99 | LSB | printed ±; Guaranteed no missed codes to 12 bits | 3 | |
| Positive Full-Scale Error | 1 | 6 | LSB | printed ± | 3 | ||
| Positive Full-Scale Error Match | 2 | 8 | LSB | printed ± | 3 | ||
| Midscale Error | 0 | 5 | 11 | LSB | printed +5 typ, 0/+11 max | 3 | |
| Midscale Error Match | 2 | 8 | LSB | printed ± | 3 | ||
| Negative Full-Scale Error | 1 | 6 | LSB | printed ± | 3 | ||
| Negative Full-Scale Error Match | 2 | 8 | LSB | printed ± | 3 | ||
| Common-Mode Voltage Range | 0.5 | 1.9 | V | 3 | |||
| DC Leakage Current | 0.5 | 5 | μA | printed ± | 3 | ||
| VREF Input Current | 0.3 | 0.45 | mA | When in reference overdrive mode | 3 | ||
| VREF Output Voltage | VREF | 2.038 | 2.058 | V | 2.048 V ± 0.5% maximum at VDD = 2.5 V ± 5% | 3 | |
| VREF Output Voltage | VREF | 2.043 | 2.053 | V | 2.048 V ± 0.25% maximum at VDD = 2.5 V ± 5% and 25°C | 3 | |
| VREF Temperature Coefficient | 6 | 20 | ppm/°C | 3 | |||
| Input Current | IIN | -1 | 1 | μA | VIN = 0 V or VDRIVE | 4 | |
| Floating-State Leakage Current | -1 | 1 | μA | 4 | |||
| Output Low Voltage | VOL | 0.2 | V | 4 | |||
| Track-and-Hold Acquisition Time | 30 | ns | Full-scale step input, settling to 0.5 LSBs | 4 | |||
| Throughput Rate | 5 | MSPS | 4 | ||||
| ITOTAL Normal Mode (Operational) | ITOTAL | 14 | 20 | mA | Digital inputs = 0 V or VDRIVE | 4 | |
| ITOTAL Normal Mode (Static) | ITOTAL | 6 | 7.8 | mA | SCLK on or off | 4 | |
| ITOTAL Partial Power-Down Mode | ITOTAL | 3.5 | 4.5 | mA | SCLK on or off | 4 | |
| ITOTAL Full Power-Down Mode | ITOTAL | 5 | 40 | μA | SCLK on or off, −40°C to +85°C | 4 | |
| Power Dissipation Normal Mode (Operational) | 36 | 59 | mW | 4 | |||
| Power Dissipation Normal Mode (Static) | 16 | 21.5 | mW | SCLK on or off | 4 | ||
| Power Dissipation Partial Power-Down Mode | 9.5 | 11.5 | mW | SCLK on or off | 4 | ||
| Power Dissipation Full Power-Down Mode | 16 | 110 | μW | SCLK on or off, −40°C to +85°C | 4 | ||
| CS to SCLK setup time | t2 | 5 | ns | 5 | |||
| Quiet time | tQUIET | 5 | ns | Minimum time between end of serial read and next falling edge of CS | 5 | ||
| Delay from CS to SDATA three-state disabled | t3 | 6 | ns | 10 pF load | 5 | ||
| Data access time | t4 | 11 | ns | 2.25 V ≤ VDRIVE < 2.75 V | 5 | ||
| Data access time | t4 | 9.5 | ns | 2.75 V ≤ VDRIVE < 3.3 V | 5 | ||
| Data access time | t4 | 9 | ns | 3.3 V ≤ VDRIVE ≤ 3.6 V | 5 | ||
| SCLK low pulse width | t5 | 5 | ns | 5 | |||
| SCLK high pulse width | t6 | 5 | ns | 5 | |||
| SCLK to data valid hold time | t7 | 3.5 | ns | 10 pF load | 5 | ||
| CS rising edge to SDATA high impedance | t8 | 9.5 | ns | 10 pF load | 5 | ||
| CS rising edge to falling edge pulse width | t9 | 5 | ns | 5 | |||
| SCLK falling edge to SDATA high impedance | t10 | 4.5 | 9.5 | ns | 10 pF load | 5 | |
| VDD to AGND, DGND, REFGND | -0.3 | 3 | V | 6 | |||
| VDRIVE to AGND, DGND, REFGND | -0.3 | 5 | V | 6 | |||
| VDD to VDRIVE | -5 | 3 | V | 6 | |||
| AGND to DGND to REFGND | -0.3 | 0.3 | V | 6 | |||
| Input Current to Any Pin Except Supply Pins | -10 | 10 | mA | printed ±10 mA | 6 | ||
| Operating Temperature Range (B Grade) | -40 | 85 | °C | B Grade | 6 | ||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Reflow Temperature | 255 | °C | 10 sec to 30 sec | 6 | |||
| ESD | 1.5 | kV | 6 | ||||
| Thermal Impedance θJA | θJA | 143 | °C/W | TSSOP | 6 | ||
| Thermal Impedance θJC | θJC | 45 | °C/W | TSSOP | 6 |
CAD (KiCad official)
- Symbol:
AD7356BRUZ - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7356bruz-etched.step/ad7356bruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7356bruz.step/ad7356bruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
48ef9265e95b67cf, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7356BRUZ
**Analog Devices** · Analog To Digital Converters (ADCs) · TSSOP-16
AD7356BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VINA+ | input | Non-inverting analog input of ADC A, forming a fully differential pair with VINA−. |
| 2 | VINA− | input | Inverting analog input of ADC A, forming a fully differential pair with VINA+. |
| 3 | REFA | bidirectional | Reference decoupling pin for ADC A (10 µF recommended to REFGND); carries the nominal 2.048 V internal reference and can be overdriven by an external reference of 2.048 V + 100 mV to VDD. |
| 4 | REFGND | power_in | Reference ground for the reference circuitry; connect to the system AGND plane, with decoupling capacitors placed between this pin and REFA/REFB. |
| 5 | AGND | power_in | Analog ground reference for all analog circuitry; AGND and DGND must not differ by more than 0.3 V, even transiently. |
| 6 | REFB | bidirectional | Reference decoupling pin for ADC B (10 µF recommended to REFGND); carries the nominal 2.048 V internal reference and can be overdriven by an external reference of 2.048 V + 100 mV to VDD. |
| 7 | VINB− | input | Inverting analog input of ADC B, forming a fully differential pair with VINB+. |
| 8 | VINB+ | input | Non-inverting analog input of ADC B, forming a fully differential pair with VINB−. |
| 9 | VDD | power_in | Power supply input, 2.5 V ± 10%, decoupled to AGND with 0.1 µF in parallel with 10 µF tantalum. |
| 10 | CS | input | Active-low chip select that initiates conversions and frames the serial data transfer. |
| 11 | AGND | power_in | Analog ground reference for all analog circuitry; AGND and DGND must not differ by more than 0.3 V, even transiently. |
| 12 | DGND | power_in | Digital ground reference for all digital circuitry; connect to the system DGND plane and keep within 0.3 V of AGND. |
| 13 | SDATAB | output | Serial data output for ADC B, MSB first, clocked out on SCLK falling edges (14 SCLK falling edges for 12 data bits after two leading zeros). |
| 14 | SDATAA | output | Serial data output for ADC A, MSB first, clocked out on SCLK falling edges (14 SCLK falling edges for 12 data bits after two leading zeros). |
| 15 | SCLK | input | Serial clock logic input for accessing data and also the clock source for the conversion process. |
| 16 | VDRIVE | power_in | Logic power supply input setting the interface voltage (2.25 V to 3.6 V per specifications), decoupled to DGND with 0.1 µF in parallel with 10 µF tantalum. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD | VDD | 2.25 | | 2.75 | V | Nominal VDD = 2.5 V | 4 |
| Logic supply VDRIVE | VDRIVE | 2.25 | | 3.6 | V | | 4 |
| Signal-to-Noise Ratio | SNR | 70 | 71.5 | | dB | fIN = 1 MHz sine wave | 3 |
| Signal-to-(Noise and Distortion) | SINAD | 69.5 | 71 | | dB | fIN = 1 MHz sine wave | 3 |
| Total Harmonic Distortion | THD | | -84 | -77.5 | dB | fIN = 1 MHz sine wave | 3 |
| Spurious Free Dynamic Range | SFDR | | -85 | -78.5 | dB | fIN = 1 MHz sine wave | 3 |
| Integral Nonlinearity | INL | | 0.5 | 1 | LSB | printed ± | 3 |
| Differential Nonlinearity | DNL | | 0.5 | 0.99 | LSB | printed ±; Guaranteed no missed codes to 12 bits | 3 |
| Positive Full-Scale Error | | | 1 | 6 | LSB | printed ± | 3 |
| Positive Full-Scale Error Match | | | 2 | 8 | LSB | printed ± | 3 |
| Midscale Error | | 0 | 5 | 11 | LSB | printed +5 typ, 0/+11 max | 3 |
| Midscale Error Match | | | 2 | 8 | LSB | printed ± | 3 |
| Negative Full-Scale Error | | | 1 | 6 | LSB | printed ± | 3 |
| Negative Full-Scale Error Match | | | 2 | 8 | LSB | printed ± | 3 |
| Common-Mode Voltage Range | | 0.5 | | 1.9 | V | | 3 |
| DC Leakage Current | | | 0.5 | 5 | μA | printed ± | 3 |
| VREF Input Current | | | 0.3 | 0.45 | mA | When in reference overdrive mode | 3 |
| VREF Output Voltage | VREF | 2.038 | | 2.058 | V | 2.048 V ± 0.5% maximum at VDD = 2.5 V ± 5% | 3 |
| VREF Output Voltage | VREF | 2.043 | | 2.053 | V | 2.048 V ± 0.25% maximum at VDD = 2.5 V ± 5% and 25°C | 3 |
| VREF Temperature Coefficient | | | 6 | 20 | ppm/°C | | 3 |
| Input Current | IIN | -1 | | 1 | μA | VIN = 0 V or VDRIVE | 4 |
| Floating-State Leakage Current | | -1 | | 1 | μA | | 4 |
| Output Low Voltage | VOL | | | 0.2 | V | | 4 |
| Track-and-Hold Acquisition Time | | | | 30 | ns | Full-scale step input, settling to 0.5 LSBs | 4 |
| Throughput Rate | | | | 5 | MSPS | | 4 |
| ITOTAL Normal Mode (Operational) | ITOTAL | | 14 | 20 | mA | Digital inputs = 0 V or VDRIVE | 4 |
| ITOTAL Normal Mode (Static) | ITOTAL | | 6 | 7.8 | mA | SCLK on or off | 4 |
| ITOTAL Partial Power-Down Mode | ITOTAL | | 3.5 | 4.5 | mA | SCLK on or off | 4 |
| ITOTAL Full Power-Down Mode | ITOTAL | | 5 | 40 | μA | SCLK on or off, −40°C to +85°C | 4 |
| Power Dissipation Normal Mode (Operational) | | | 36 | 59 | mW | | 4 |
| Power Dissipation Normal Mode (Static) | | | 16 | 21.5 | mW | SCLK on or off | 4 |
| Power Dissipation Partial Power-Down Mode | | | 9.5 | 11.5 | mW | SCLK on or off | 4 |
| Power Dissipation Full Power-Down Mode | | | 16 | 110 | μW | SCLK on or off, −40°C to +85°C | 4 |
| CS to SCLK setup time | t2 | 5 | | | ns | | 5 |
| Quiet time | tQUIET | 5 | | | ns | Minimum time between end of serial read and next falling edge of CS | 5 |
| Delay from CS to SDATA three-state disabled | t3 | | | 6 | ns | 10 pF load | 5 |
| Data access time | t4 | | | 11 | ns | 2.25 V ≤ VDRIVE < 2.75 V | 5 |
| Data access time | t4 | | | 9.5 | ns | 2.75 V ≤ VDRIVE < 3.3 V | 5 |
| Data access time | t4 | | | 9 | ns | 3.3 V ≤ VDRIVE ≤ 3.6 V | 5 |
| SCLK low pulse width | t5 | 5 | | | ns | | 5 |
| SCLK high pulse width | t6 | 5 | | | ns | | 5 |
| SCLK to data valid hold time | t7 | 3.5 | | | ns | 10 pF load | 5 |
| CS rising edge to SDATA high impedance | t8 | | | 9.5 | ns | 10 pF load | 5 |
| CS rising edge to falling edge pulse width | t9 | 5 | | | ns | | 5 |
| SCLK falling edge to SDATA high impedance | t10 | 4.5 | | 9.5 | ns | 10 pF load | 5 |
| VDD to AGND, DGND, REFGND | | -0.3 | | 3 | V | | 6 |
| VDRIVE to AGND, DGND, REFGND | | -0.3 | | 5 | V | | 6 |
| VDD to VDRIVE | | -5 | | 3 | V | | 6 |
| AGND to DGND to REFGND | | -0.3 | | 0.3 | V | | 6 |
| Input Current to Any Pin Except Supply Pins | | -10 | | 10 | mA | printed ±10 mA | 6 |
| Operating Temperature Range (B Grade) | | -40 | | 85 | °C | B Grade | 6 |
| Storage Temperature Range | | -65 | | 150 | °C | | 6 |
| Junction Temperature | | | | 150 | °C | | 6 |
| Reflow Temperature | | | | 255 | °C | 10 sec to 30 sec | 6 |
| ESD | | | | 1.5 | kV | | 6 |
| Thermal Impedance θJA | θJA | | 143 | | °C/W | TSSOP | 6 |
| Thermal Impedance θJC | θJC | | 45 | | °C/W | TSSOP | 6 |
## CAD (KiCad official)
- Symbol: `AD7356BRUZ`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad7356bruz-etched.step` / `ad7356bruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7356bruz.step` / `ad7356bruz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7356.pdf) (20 pp, sha256 `48ef9265e95b67cf`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7356bruz-datasheet.pdf)