component
AD7328BRUZ-REEL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ad7328bruz-reel7",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Analog To Digital Converters (ADCs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"data converters",
"ad7328bruz-reel7",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
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"README.md",
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"ad7328bruz-reel7.step",
"ad7328bruz-reel7.lbr",
"docs/hero.png",
"docs/ad7328bruz-reel7-datasheet.pdf",
"viewers/symbol.html",
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"ad7328bruz-reel7-hero.overlay.json",
"ad7328bruz-reel7-etched.glb"
],
"component": {
"mpn": "AD7328BRUZ-REEL7",
"manufacturer": "Analog Devices",
"package": "TSSOP-20",
"pin_count": 20,
"category": "Data Converters",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7328.pdf",
"parts": {
"symbol": "ad7328bruz-reel7.kicad_sym",
"footprint": "ad7328bruz-reel7.kicad_mod",
"model_3d": "ad7328bruz-reel7-hero.glb",
"model_3d_plain": "ad7328bruz-reel7-etched.glb",
"model_3d_step": "ad7328bruz-reel7-etched.step",
"model_3d_step_plain": "ad7328bruz-reel7.step",
"lbr": "ad7328bruz-reel7.lbr"
},
"distributor_links": {
"lcsc": "C578422",
"digikey": "AD7328BRUZ-REEL7TR-ND",
"mouser": "584-AD7328BRUZ-R7"
},
"distributor_check": {
"checked_at": "2026-10-30T15:57:50Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "AD7328BRUZ-REEL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD7328BRUZ-R7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "CS",
"type": "input",
"description": "Active-low chip select that initiates conversions on the AD7328 and frames the serial data transfer."
},
{
"number": "2",
"name": "DIN",
"type": "input",
"description": "Data input for writing to the on-chip registers, clocked into the register on the falling edge of SCLK."
},
{
"number": "3",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference for all digital circuitry; DGND and AGND should ideally be at the same potential and must not be more than 0.3 V apart, even transiently."
},
{
"number": "4",
"name": "AGND",
"type": "power_in",
"description": "Analog ground reference for all analog circuitry; analog inputs and any external reference must be referred to AGND, and AGND must not be more than 0.3 V from DGND, even transiently."
},
{
"number": "5",
"name": "REFIN/OUT",
"type": "bidirectional",
"description": "Reference input/output: the internal 2.5 V reference appears here and requires a 680 nF capacitor, or an external reference can be applied if the internal reference is disabled; external reference mode is the power-up default."
},
{
"number": "6",
"name": "VSS",
"type": "power_in",
"description": "Negative power supply voltage for the analog input section."
},
{
"number": "7",
"name": "VIN0",
"type": "passive",
"description": "Analog input channel 0 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "8",
"name": "VIN1",
"type": "passive",
"description": "Analog input channel 1 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "9",
"name": "VIN4",
"type": "passive",
"description": "Analog input channel 4 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "10",
"name": "VIN5",
"type": "passive",
"description": "Analog input channel 5 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "11",
"name": "VIN7",
"type": "passive",
"description": "Analog input channel 7 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "12",
"name": "VIN6",
"type": "passive",
"description": "Analog input channel 6 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "13",
"name": "VIN3",
"type": "passive",
"description": "Analog input channel 3 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "14",
"name": "VIN2",
"type": "passive",
"description": "Analog input channel 2 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference)."
},
{
"number": "15",
"name": "VDD",
"type": "power_in",
"description": "Positive power supply voltage for the analog input section."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Analog supply for the ADC core, rated 2.7 V to 5.25 V with specifications applying from 4.75 V to 5.25 V, and should be decoupled to AGND."
},
{
"number": "17",
"name": "VDRIVE",
"type": "power_in",
"description": "Logic power supply input that sets the interface operating voltage; it should be decoupled to DGND and must not exceed VCC by more than 0.3 V."
},
{
"number": "18",
"name": "DOUT",
"type": "output",
"description": "Serial data output that clocks out on the falling edge of SCLK, requiring 16 SCLKs to access the MSB-first data stream of three channel ID bits, a sign bit and 12 conversion bits."
},
{
"number": "19",
"name": "DGND",
"type": "power_in",
"description": "Digital ground pin, internally common with DGND pin 3, referenced to AGND within 0.3 V."
},
{
"number": "20",
"name": "SCLK",
"type": "input",
"description": "Serial clock logic input used to access data from the AD7328 and as the clock source for the conversion process."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin 19 DGND is listed on the same Table 5 row as pin 3 ('3, 19 DGND'), so the pin is treated as a se; The VIN0-VIN7 pin assignments come from the Table 5 ordered list (7, 8, 14, 13, 9, 10, 12, 11) becau; The datasheet's ordering guide confirms AD7328BRUZ-REEL7 is the 20-lead TSSOP RU-20 package; the ree"
],
"pages_sent": 7,
"cost_usd": 0.0621,
"at": "2026-10-30T15:57:30"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7328.pdf",
"pages": 36,
"sha256": "67cff22d2bc81382",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 20,
"described": 20,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad7328bruz-reel7.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
6.5,
1.2
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad7328bruz-reel7-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
6.5,
1.2
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "6686c36e0e7f778829bfe55c76f361f468c991c611b3057c2cd4eb976b8e48dd",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "RU-20",
"source_page": 34,
"D": {
"nom_mm": 6.5,
"range_mm": [
6.4,
6.6
]
},
"E1": {
"nom_mm": 4.4,
"range_mm": [
4.3,
4.5
]
},
"E": {
"nom_mm": 6.4,
"range_mm": [
null,
null
]
},
"e": {
"nom_mm": 0.65,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 1.2,
"range_mm": [
null,
1.2
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ad7328bruz-reel7.step",
"verdict": "PASS",
"reasons": [
"height and body within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}