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AD7328BRUZ-REEL7

Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-20

AD7328BRUZ-REEL7 from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Active-low chip select that initiates conversions on the AD7328 and frames the serial data transfer.
2 DIN input Data input for writing to the on-chip registers, clocked into the register on the falling edge of SCLK.
3 DGND power_in Digital ground reference for all digital circuitry; DGND and AGND should ideally be at the same potential and must not be more than 0.3 V apart, even transiently.
4 AGND power_in Analog ground reference for all analog circuitry; analog inputs and any external reference must be referred to AGND, and AGND must not be more than 0.3 V from DGND, even transiently.
5 REFIN/OUT bidirectional Reference input/output: the internal 2.5 V reference appears here and requires a 680 nF capacitor, or an external reference can be applied if the internal reference is disabled; external reference mode is the power-up default.
6 VSS power_in Negative power supply voltage for the analog input section.
7 VIN0 passive Analog input channel 0 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
8 VIN1 passive Analog input channel 1 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
9 VIN4 passive Analog input channel 4 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
10 VIN5 passive Analog input channel 5 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
11 VIN7 passive Analog input channel 7 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
12 VIN6 passive Analog input channel 6 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
13 VIN3 passive Analog input channel 3 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
14 VIN2 passive Analog input channel 2 into the on-chip track-and-hold, selected via ADD2-ADD0 and configurable with the mode bits and per-channel input range registers (±10 V, ±5 V, ±2.5 V, 0 V to +10 V with a +2.5 V reference).
15 VDD power_in Positive power supply voltage for the analog input section.
16 VCC power_in Analog supply for the ADC core, rated 2.7 V to 5.25 V with specifications applying from 4.75 V to 5.25 V, and should be decoupled to AGND.
17 VDRIVE power_in Logic power supply input that sets the interface operating voltage; it should be decoupled to DGND and must not exceed VCC by more than 0.3 V.
18 DOUT output Serial data output that clocks out on the falling edge of SCLK, requiring 16 SCLKs to access the MSB-first data stream of three channel ID bits, a sign bit and 12 conversion bits.
19 DGND power_in Digital ground pin, internally common with DGND pin 3, referenced to AGND within 0.3 V.
20 SCLK input Serial clock logic input used to access data from the AD7328 and as the clock source for the conversion process.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category Data Converters
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-Noise Ratio (SNR), differential mode 76 dB fIN = 50 kHz sine wave; differential mode 3
Signal-to-Noise Ratio (SNR), single-ended/pseudo differential mode 72.5 dB fIN = 50 kHz sine wave; single-ended/pseudo differential mode 3
SINAD, differential mode, ±2.5 V and ±5 V ranges 75 dB fIN = 50 kHz; differential mode; ±2.5 V and ±5 V ranges 3
SINAD, differential mode, 0 V to +10 V and ±10 V ranges 76 dB fIN = 50 kHz; differential mode; 0 V to +10 V and ±10 V ranges 3
SINAD, single-ended/pseudo differential, ±2.5 V and ±5 V ranges 72 dB fIN = 50 kHz; single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 3
SINAD, single-ended/pseudo differential, 0 V to +10 V and ±10 V ranges 72.5 dB fIN = 50 kHz; single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges 3
Total Harmonic Distortion (THD), differential, ±2.5 V and ±5 V ranges -80 dB fIN = 50 kHz; differential mode; ±2.5 V and ±5 V ranges 3
Total Harmonic Distortion (THD), differential, 0 V to +10 V and ±10 V ranges -82 dB fIN = 50 kHz; differential mode; 0 V to +10 V and ±10 V ranges 3
Total Harmonic Distortion (THD), single-ended/pseudo differential, ±2.5 V and ±5 V ranges -77 dB fIN = 50 kHz; single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 3
Total Harmonic Distortion (THD), single-ended/pseudo differential, 0 V to +10 V and ±10 V ranges -80 dB fIN = 50 kHz; single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges 3
Peak Harmonic or Spurious Noise (SFDR), differential, ±2.5 V and ±5 V ranges -80 dB fIN = 50 kHz; differential mode; ±2.5 V and ±5 V ranges 3
Peak Harmonic or Spurious Noise (SFDR), differential, 0 V to +10 V and ±10 V ranges -82 dB fIN = 50 kHz; differential mode; 0 V to +10 V and ±10 V ranges 3
Peak Harmonic or Spurious Noise (SFDR), single-ended/pseudo differential, ±2.5 V and ±5 V ranges -78 dB fIN = 50 kHz; single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges 3
Peak Harmonic or Spurious Noise (SFDR), single-ended/pseudo differential, 0 V to +10 V and ±10 V ranges -79 dB fIN = 50 kHz; single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges 3
Integral Nonlinearity (INL), differential mode -1.1 1.1 LSB Differential mode 3
Integral Nonlinearity (INL), single-ended/pseudo differential mode -1 1 LSB Single-ended/pseudo differential mode 3
Integral Nonlinearity (INL), single-ended/pseudo differential mode, LSB = FSR/8192 -0.7 1.2 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) 3
Differential Nonlinearity (DNL), differential mode -0.9 1.5 LSB Differential mode; guaranteed no missing codes to 13 bits 4
Differential Nonlinearity (DNL), single-ended mode -0.9 0.9 LSB Single-ended mode; guaranteed no missing codes to 12 bits 4
Differential Nonlinearity (DNL), single-ended/pseudo differential mode, LSB = FSR/8192 -0.7 1 LSB Single-ended/pseudo differential mode (LSB = FSR/8192) 4
Offset Error, single-ended/pseudo differential mode -4 9 LSB Single-ended/pseudo differential mode 4
Offset Error, differential mode -7 10 LSB Differential mode 4
Gain Error, single-ended/pseudo differential mode -8 8 LSB Single-ended/pseudo differential mode 4
Gain Error, differential mode -14 14 LSB Differential mode 4
Positive Full-Scale Error, single-ended/pseudo differential mode -4 4 LSB Single-ended/pseudo differential mode 4
Positive Full-Scale Error, differential mode -7 7 LSB Differential mode 4
Bipolar Zero Code Error, single-ended/pseudo differential mode -8.5 8.5 LSB Single-ended/pseudo differential mode 4
Bipolar Zero Code Error, differential mode -7.5 7.5 LSB Differential mode 4
Negative Full-Scale Error, single-ended/pseudo differential mode -4 4 LSB Single-ended/pseudo differential mode 4
Negative Full-Scale Error, differential mode -6 6 LSB Differential mode 4
Pseudo Differential VIN(−) Input Range, ±3.5 V VIN(−) -3.5 3.5 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; Reference = 2.5 V; range = ±10 V 4
Pseudo Differential VIN(−) Input Range, ±6 V VIN(−) -6 6 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; Reference = 2.5 V; range = ±5 V 4
Pseudo Differential VIN(−) Input Range, ±5 V VIN(−) -5 5 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; Reference = 2.5 V; range = ±2.5 V 4
Pseudo Differential VIN(−) Input Range, +3/−5 V VIN(−) -5 3 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; Reference = 2.5 V; range = 0 V to +10 V 4
DC Leakage Current -200 200 nA VIN = VDD or VSS 4
Input Voltage Range, reference input 2.5 3 V 4
Reference Output Voltage Error at 25°C -5 5 mV 4
Reference Output Voltage Error, TMIN to TMAX -10 10 mV TMIN to TMAX 4
Reference Temperature Coefficient 25 ppm/°C 4
Output Voltage Hysteresis 50 ppm 4
Input High Voltage VINH 2.4 V 5
Input Low Voltage VINL 0.8 V VCC = 4.75 V to 5.25 V 5
Input Low Voltage VINL 0.4 V VCC = 2.7 to 3.6 V 5
Input Current IIN -1 1 µA VIN = 0 V or VDRIVE 5
Output Low Voltage VOL 0.4 V ISINK = 200 µA 5
VDD supply voltage VDD 12 16.5 V See Table 6 5
VSS supply voltage VSS -16.5 -12 V See Table 6 5
VCC supply voltage VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V 5
VDRIVE supply voltage VDRIVE 2.7 5.25 V 5
Normal Mode (Operational) IDD IDD 360 µA Normal mode (operational), fS = 1 MSPS; VDD = 16.5 V 5
Normal Mode (Operational) ISS ISS 410 µA Normal mode (operational), fS = 1 MSPS; VSS = −16.5 V 5
Normal Mode (Operational) ICC and IDRIVE ICC and IDRIVE 3.4 mA Normal mode (operational), fS = 1 MSPS; VCC/VDRIVE = 5.25 V 5
VDD to AGND, DGND VDD -0.3 16.5 V To AGND, DGND 7
VSS to AGND, DGND VSS -16.5 0.3 V To AGND, DGND 7
VCC to AGND, DGND VCC -0.3 7 V To AGND, DGND 7
VDRIVE to AGND, DGND VDRIVE -0.3 7 V To AGND, DGND 7
Input Current to Any Pin Except Supplies -10 10 mA Any pin except supplies 7
Operating Temperature Range -40 85 °C 7
Thermal Impedance θJA, TSSOP package θJA 143 °C/W TSSOP package 7
Thermal Impedance θJC, TSSOP package θJC 45 °C/W TSSOP package 7

CAD (KiCad official)

  • Symbol: AD7328BRUZ-REEL7
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad7328bruz-reel7-etched.step / ad7328bruz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7328bruz-reel7.step / ad7328bruz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 67cff22d2bc81382, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF