AD7304BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTB	output	Channel B rail-to-rail buffered DAC voltage output, full-scale set by the voltage on VREFB, and open circuit when SHDN is enabled.
2	VOUTA	output	Channel A rail-to-rail buffered DAC voltage output, full-scale set by the voltage on VREFA, and open circuit when SHDN is enabled.
3	VSS	power_in	Negative power supply input with a specified operating range of 0 V to -5.5 V.
4	VREFA	input	Channel A reference input that sets the VOUTA full-scale voltage, specified for VSS < VREFA < VDD.
5	VREFB	input	Channel B reference input that sets the VOUTB full-scale voltage, specified for VSS < VREFB < VDD.
6	GND	power_in	Common analog and digital ground.
7	LDAC	input	Active-low asynchronous load DAC register strobe that transfers all four input registers to the DAC registers, which are transparent when LDAC = 0.
8	CLR	input	Active-low asynchronous input that clears all input and DAC registers to zero and does not affect the serial register.
9	CS	input	Active-low chip select that disables shift register loading when high and transfers serial data to the decoded input register when it returns high.
10	CLK	input	Clock input whose positive edge clocks data into the shift register, disabled by CS.
11	SDI/SHDN	input	Serial data input loaded MSB first into the shift register, also the hardware shutdown control that is active when the pin is left floating by a three-state driver.
12	VREFD	input	Channel D reference input that sets the VOUTD full-scale voltage, specified for VSS < VREFD < VDD.
13	VREFC	input	Channel C reference input that sets the VOUTC full-scale voltage, specified for VSS < VREFC < VDD.
14	VDD	power_in	Positive power supply input with a specified operating range of 2.7 V to 5.5 V.
15	VOUTD	output	Channel D rail-to-rail buffered DAC voltage output, full-scale set by the voltage on VREFD, and open circuit when SHDN is enabled.
16	VOUTC	output	Channel C rail-to-rail buffered DAC voltage output, full-scale set by the voltage on VREFC, and open circuit when SHDN is enabled.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Interface ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resolution	N		8		Bits	3 V/5 V/±5 V ±10%	3
Integral Nonlinearity	INL	-1		1	LSB	3 V/5 V/±5 V ±10%	3
Differential Nonlinearity	DNL	-1		1	LSB	Monotonic, all codes 0 to 0xFF; 3 V/5 V/±5 V ±10%	3
Zero-Scale Error	VZSE			15	mV	Data = 0x00; 3 V/5 V/±5 V ±10%	3
Full-Scale Voltage Error	VFSE	-4		4	LSB	Data = 0xFF; 3 V/5 V/±5 V ±10%	3
Full-Scale Temperature Coefficient	TCVFS		5		ppm/°C	3 V/5 V/±5 V ±10%	3
Input Resistance (AD7304)	RREFIN		28		kΩ	Code = 0x55	3
Input Capacitance, reference	CREFIN		5		pF		3
Output Current Drive	IOUT		3		mA	Code = 0x80, ∆VOUT < 1 LSB; typ is ±3	3
Shutdown Resistance	ROUT		120		kΩ	DAC outputs placed in shutdown state	3
Capacitive Load	CL		200		pF	No oscillation	3
Logic Input Low Voltage	VIL			0.6	V	3 V ± 10%	3
Logic Input Low Voltage	VIL			0.8	V	5 V ± 10% and ±5 V ± 10%	3
Logic Input High Voltage	VIH	2.1			V	3 V ± 10%	3
Logic Input High Voltage	VIH	2.4			V	5 V ± 10% and ±5 V ± 10%	3
Input Leakage Current	IIL	-10		10	µA	SDI/SHDN pin has 30 µA maximum	3
Output Slew Rate	SR	1	2.7		V/µs	Code = 0x00 to 0xFF to 0x00; 3 V ± 10%	3
Output Slew Rate	SR	1	3.6		V/µs	Code = 0x00 to 0xFF to 0x00; 5 V ± 10% and ±5 V ± 10%	3
Settling Time	tS		1.1	2	µs	To ±0.1% of full scale; 3 V ± 10%	3
Settling Time	tS		1	2	µs	To ±0.1% of full scale; 5 V ± 10% and ±5 V ± 10%	3
Shutdown Recovery Time	tSDR			2	µs	To ±0.1% of full scale	3
Time to Shutdown	tSDN		15		µs		3
Feedthrough	VOUT/VREF		-65		dB	Code = 0x00, VREF = 1 V p-p, f = 100 kHz	3
Positive Supply Current	IDD			6	mA	VLOGIC = 0 V or VDD, no load	3
Negative Supply Current	ISS			6	mA	VSS = -5 V	3
Power Dissipation	PDISS			15	mW	VLOGIC = 0 V or VDD, no load; 3 V ± 10%	3
Power Dissipation	PDISS			30	mW	VLOGIC = 0 V or VDD, no load; 5 V ± 10%	3
Power Dissipation	PDISS			60	mW	VLOGIC = 0 V or VDD, no load; ±5 V ± 10%	3
Power Down Current	IDD_SD		40		µA	SDI/SHDN = floating	3
Clock Width High	tCH	70			ns	3 V ± 10%	4
Clock Width High	tCH	55			ns	5 V ± 10% and ±5 V ± 10%	4
Clock Width Low	tCL	70			ns	3 V ± 10%	4
Clock Width Low	tCL	55			ns	5 V ± 10% and ±5 V ± 10%	4
Data Setup	tDS	50			ns	3 V ± 10%	4
Data Setup	tDS	40			ns	5 V ± 10% and ±5 V ± 10%	4
Data Hold	tDH	30			ns	3 V ± 10%	4
Data Hold	tDH	20			ns	5 V ± 10% and ±5 V ± 10%	4
Load Pulse Width	tLDW	70			ns	3 V ± 10%	4
Load Pulse Width	tLDW	60			ns	5 V ± 10% and ±5 V ± 10%	4
Load Setup	tLD1	40			ns	3 V ± 10%	4
Load Setup	tLD1	30			ns	5 V ± 10% and ±5 V ± 10%	4
Load Hold	tLD2	40			ns	3 V ± 10%	4
Load Hold	tLD2	30			ns	5 V ± 10% and ±5 V ± 10%	4
Clear Pulse Width	tCLWR	60			ns	3 V/5 V/±5 V ±10%	4
Select	tCSS	30			ns	3 V ± 10%	4
Select	tCSS	20			ns	5 V ± 10% and ±5 V ± 10%	4
Deselect	tCSH	60			ns	3 V ± 10%	4
Deselect	tCSH	40			ns	5 V ± 10% and ±5 V ± 10%	4
VDD to GND	VDD	-0.3		8	V		5
VSS to GND	VSS	-8		0.3	V	printed +0.3 V, -8 V	5
Logic Inputs to GND		-0.3			V	upper limit printed as VDD + 0.3 V	5
VOUTX to GND	VOUTX	-0.3			V	upper limit printed as VDD + 0.3 V	5
IOUT Short-Circuit to GND	IOUT			50	mA		5
Thermal Resistance, 16-Lead TSSOP (RU-16)	θJA		180		°C/W		5
Maximum Junction Temperature	TJ MAX			150	°C		5
Operating Temperature Range		-40		85	°C		5
Storage Temperature Range		-65		150	°C		5

CAD (KiCad official)

Symbol: AD7304BRUZ
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad7304bruz-etched.step / ad7304bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7304bruz.step / ad7304bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (20 pp, sha256 204a8502e7f12c73, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7304BRUZ

Verified AD7304BRUZ

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3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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