# AD7303BRZ

**Analog Devices** · Digital To Analog Converters (DACs) · SOIC-8

AD7303BRZ from Analog Devices, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT A | output | Analog output voltage from DAC A, with an output amplifier that swings rail to rail. |
| 2 | VDD | power_in | Power supply input operating from +2.7 V to +5.5 V, which should be decoupled to GND. |
| 3 | GND | power_in | Ground reference point for all circuitry on the part. |
| 4 | REF | bidirectional | External reference input for both DACs with range 1 V to VDD/2 when INT/EXT bit is set to logic one, and outputs the internal reference voltage for decoupling when the internal reference is selected (do not connect external voltages then). |
| 5 | SCLK | input | Serial clock logic input; data is clocked into the input shift register on the rising edge at rates up to 30 MHz. |
| 6 | DIN | input | Serial data input to the 16-bit shift register (8 data bits and 8 control bits), clocked in on the rising edge of the clock. |
| 7 | SYNC | input | Active-low level-triggered frame synchronization input that enables the input shift register when low, with the rising edge updating the relevant registers. |
| 8 | VOUT B | output | Analog output voltage from DAC B, with an output amplifier that swings rail to rail. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-8 |
| Category | Data Converters |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy |  | -1 |  | 1 | LSB | Note 2 | 2 |
| Differential Nonlinearity |  | -1 |  | 1 | LSB | Guaranteed Monotonic | 2 |
| Zero-Code Error |  |  |  | 3 | LSB | @ +25°C, All Zeros Loaded to DAC Register | 2 |
| Internal Voltage Reference Error |  | -1 |  | 1 | % |  | 2 |
| Output Voltage Settling Time |  |  | 1.2 | 2 | µs | Typically 1.2 µs | 2 |
| Power Supply Rejection Ratio |  |  |  | 0.0001 | %/% | ΔVDD = ±10% | 2 |
| Input Current |  | -10 |  | 10 | µA |  | 2 |
| Input Low Voltage | VINL |  |  | 0.8 | V | VDD = +5 V | 2 |
| Input Low Voltage | VINL |  |  | 0.6 | V | VDD = +3 V | 2 |
| Input High Voltage | VINH | 2.4 |  |  | V | VDD = +5 V | 2 |
| Input High Voltage | VINH | 2.1 |  |  | V | VDD = +3 V | 2 |
| Pin Capacitance |  |  |  | 5 | pF |  | 2 |
| Supply Voltage | VDD | 2.7 |  | 5.5 | V |  | 2 |
| IDD Normal Mode | IDD |  |  | 2.1 | mA | VDD = 3.3 V, @ +25°C, Both DACs Active, VIH = VDD, VIL = GND | 2 |
| IDD Normal Mode | IDD |  |  | 2.3 | mA | VDD = 3.3 V, TMIN, TMAX | 2 |
| IDD Normal Mode | IDD |  |  | 2.7 | mA | VDD = 5.5 V, @ +25°C | 2 |
| IDD Normal Mode | IDD |  |  | 3.5 | mA | VDD = 5.5 V, TMIN, TMAX | 2 |
| IDD Full Power-Down | IDD |  |  | 1 | µA | TMIN, TMAX, VIH = VDD, VIL = GND | 2 |
| IDD Full Power-Down | IDD |  | 80 |  | nA | @ +25°C, VIH = VDD, VIL = GND | 2 |
| Resolution |  |  | 8 |  | Bits |  | 2 |
| Full-Scale Error |  |  | -0.5 |  | LSB | All Ones Loaded to DAC Register | 2 |
| Gain Error |  |  | 1 |  | % FSR |  | 2 |
| Zero-Code Temperature Coefficient |  |  | 100 |  | µV/°C |  | 2 |
| REFIN Input Impedance |  |  | 10 |  | MΩ |  | 2 |
| Slew Rate |  |  | 7.5 |  | V/µs |  | 2 |
| DC Output Impedance |  |  | 40 |  | Ω |  | 2 |
| Short Circuit Current |  |  | 14 |  | mA |  | 2 |
| SCLK Cycle Time | t1 | 33 |  |  | ns |  | 3 |
| SCLK High Time | t2 | 13 |  |  | ns |  | 3 |
| SCLK Low Time | t3 | 13 |  |  | ns |  | 3 |
| SYNC Setup Time | t4 | 5 |  |  | ns |  | 3 |
| Data Setup Time | t5 | 5 |  |  | ns |  | 3 |
| Data Hold Time | t6 | 4.5 |  |  | ns |  | 3 |
| SYNC Hold Time | t7 | 4.5 |  |  | ns |  | 3 |
| Minimum SYNC High Time | t8 | 33 |  |  | ns |  | 3 |
| VDD to GND | VDD | -0.3 |  | 7 | V | TA = +25°C | 4 |
| Reference Input Voltage to GND |  | -0.3 |  |  | V | max is VDD + 0.3 V | 4 |
| Digital Input Voltage to GND |  | -0.3 |  |  | V | max is VDD + 0.3 V | 4 |
| VOUT A, VOUT B to GND |  | -0.3 |  |  | V | max is VDD + 0.3 V | 4 |
| Operating Temperature Range |  | -40 |  | 105 | °C | B Version | 4 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 4 |
| Junction Temperature |  |  |  | 150 | °C |  | 4 |
| SOIC Package Power Dissipation |  |  |  | 450 | mW | SOIC Package | 4 |
| SOIC Thermal Impedance | θJA |  | 157 |  | °C/W | SOIC Package | 4 |
| Lead Temperature Soldering Vapor Phase |  |  |  | 215 | °C | 60 sec | 4 |
| Lead Temperature Soldering Infrared |  |  |  | 220 | °C | 15 sec | 4 |

## CAD (KiCad official)

- Symbol: `AD7303BRZ`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `ad7303brz-etched.step` / `ad7303brz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7303brz.step` / `ad7303brz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7303.pdf) (16 pp, sha256 `7c123e5860c46c71`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7303brz-datasheet.pdf)