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Analog Devices Analog To Digital Converters (ADCs), LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7298BCPZ-RL7

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-20(4x4)

AD7298BCPZ-RL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN3	input	Analog input channel 3, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
2	VIN4	input	Analog input channel 4, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
3	VIN5	input	Analog input channel 5, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
4	VIN6	input	Analog input channel 6, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
5	VIN7	input	Analog input channel 7, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
6	GND1	power_in	Ground reference for the internal reference circuitry and all analog inputs; must be within 0.3 V of GND and connected to the system GND plane, with VREF decoupled to it by 10 μF.
7	VREF	power_in	Internal 2.5 V reference output, which can be buffered and used externally, or disabled and driven by an external reference of 2.0 V to 2.5 V; decouple with 10 μF to GND1.
8	DCAP	passive	Decoupling capacitor pin for the internal LDO, requiring 1 μF recommended capacitors to GND.
9	GND	power_in	Ground reference for all analog and digital circuitry, which must be within 0.3 V of GND1 and connected to the system ground plane.
10	VDD	power_in	Main supply voltage of 2.8 V to 3.6 V, to be decoupled to GND with 10 μF and 100 nF capacitors.
11	CS	input	Active-low chip select; the falling edge starts a conversion and frames the serial transfer, with DOUT enabled while CS is low.
12	TSENSE_BUSY	output	Busy output that goes high when a temperature sensor conversion starts and stays high until it completes.
13	DIN	input	Serial data input for writing the control register, clocked in on the falling edge of SCLK.
14	DOUT	output	Serial data output carrying four channel address bits followed by 12 bits of MSB-first conversion data, clocked out on the falling edge of SCLK.
15	SCLK	input	Serial clock input for accessing conversion data from the AD7298 (fSCLK up to 20 MHz per Table 1 conditions).
16	VDRIVE	power_in	Logic supply that sets the digital interface voltage; range 1.65 V to 3.6 V, may be lower than VDD but must not exceed VDD by more than 0.3 V, and should be decoupled to GND.
17	PD/RST	input	Power-down pin that places the part in full power-down when held low beyond 100 ns, and resets the device when pulsed low for 1 ns to 100 ns; analog inputs must be at 0 V before power-down.
18	VIN0	input	Analog input channel 0, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
19	VIN1	input	Analog input channel 1, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
20	VIN2	input	Analog input channel 2, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-20(4x4)
Category	ADC/DAC/Data Conversion
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD supply voltage	VDD	2.8	3	3.6	V		4
VDRIVE logic supply voltage	VDRIVE	1.65	3	3.6	V		4
Normal mode (operational) total supply current	ITOTAL		5.8	6.3	mA	VDD = 3.6 V, VDRIVE = 3.6 V	4
Normal mode (static) total supply current	ITOTAL		4.1	4.6	mA	VDD = 3.6 V, VDRIVE = 3.6 V	4
Partial power-down total supply current	ITOTAL		2.7	3.3	mA	VDD = 3.6 V, VDRIVE = 3.6 V	4
Full power-down total supply current	ITOTAL		1	1.6	μA	TA = −40°C to +25°C	4
Power dissipation, normal mode (operational)			17.4	18.9	mW	VDD = 3 V, VDRIVE = 3 V	4
Power dissipation, normal mode (static)			14.8	16.6	mW		4
Power dissipation, partial power-down mode			9.8	11.9	mW		4
Power dissipation, full power-down mode			3.6	5.8	μW	TA = −40°C to +25°C	4
Signal-to-noise ratio	SNR	70	72		dB	fIN = 50 kHz sine wave	3
Signal-to-noise and distortion ratio	SINAD	70	71		dB	fIN = 50 kHz sine wave	3
Total harmonic distortion	THD		-82	-77	dB	fIN = 50 kHz sine wave	3
Spurious-free dynamic range	SFDR		-84	-77.5	dB	fIN = 50 kHz sine wave	3
Integral nonlinearity	INL	-1	0.5	1	LSB		3
Differential nonlinearity	DNL	-0.99	0.5	0.99	LSB	Guaranteed no missed codes to 12 bits	3
Offset error		-4.5	2	4.5	LSB		3
Offset error matching		-4.5	2.5	4.5	LSB		3
Gain error		-4	1	4	LSB		3
Gain error matching		-2.5	1	2.5	LSB		3
Analog input DC leakage current		-1	0.01	1	μA		3
Reference output voltage		2.4925	2.5	2.5075	V	±0.3% maximum @ 25°C	3
Reference input voltage range		1		2.5	V		3
Reference DC leakage current		-1	0.01	1	μA	External reference applied to Pin VREF	3
VREF temperature coefficient			12	35	ppm/°C		3
Logic input current	IIN	-1	0.01	1	μA	VIN = 0 V or VDRIVE	4
Floating state leakage current		-1	0.01	1	μA		4
Internal temperature sensor accuracy		-2	1	2	°C	TA = −40°C to +85°C	4
Internal temperature sensor accuracy		-3	1	3	°C	TA = +85°C to +125°C	4
Internal temperature sensor operating range		-40		125	°C		4
Conversion time, temperature sensor channel	tCONVERT			100	μs	Temperature sensor channel	5
Frequency of external serial clock (minimum)	fSCLK	50			kHz	Frequency of external serial clock	5
Frequency of external serial clock (maximum)	fSCLK			20	MHz	Frequency of external serial clock	5
Quiet time between end of serial read and start of next conversion	tQUIET	6			ns	Repeat and nonrepeat mode	5
CS to SCLK setup time	t2	10			ns		5
Delay from CS falling edge until DOUT three-state disabled	t3			15	ns		5
Data access time after SCLK falling edge	t4			35	ns	VDRIVE = 1.65 V to 3 V	5
Data access time after SCLK falling edge	t4			28	ns	VDRIVE = 3 V to 3.6 V	5
SCLK to DOUT valid hold time	t7	14			ns		5
SCLK falling edge to DOUT high impedance	t8	16		34	ns		5
DIN setup time prior to SCLK falling edge	t9	5			ns		5
DIN hold time after SCLK falling edge	t10	4			ns		5
TSENSE_BUSY falling edge to CS falling edge	t11	100			ns		5
Delay from CS rising edge to DOUT high impedance	t12			30	ns		5
Internal reference power-up time from full power-down	tPOWER-UP			6	ms		5
VDD to GND	VDD	-0.3		5	V		6
VDRIVE to GND	VDRIVE	-0.3		5	V		6
Analog input voltage to GND1		-0.3		3	V		6
VREF to GND1	VREF	-0.3		3	V		6
GND1 to GND		-0.3		0.3	V		6
Input current to any pin except supplies		-10		10	mA		6
Operating temperature range		-40		125	°C		6
Storage temperature range		-65		150	°C		6
Junction temperature				150	°C		6
Pb-free soldering reflow temperature				260	°C		6
Thermal resistance, junction-to-ambient	θJA		52		°C/W	20-Lead LFCSP	6
Thermal resistance, junction-to-case	θJC		6.5		°C/W	20-Lead LFCSP	6

CAD (KiCad official)

Symbol: AD7298BCPZ-RL7
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
3D model files: ad7298bcpz-rl7-etched.step / ad7298bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7298bcpz-rl7.step / ad7298bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 aa6164eb83a61130, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7298BCPZ-RL7

**Analog Devices** · Analog To Digital Converters (ADCs) · LFCSP-20(4x4)

AD7298BCPZ-RL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN3 | input | Analog input channel 3, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 2 | VIN4 | input | Analog input channel 4, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 3 | VIN5 | input | Analog input channel 5, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 4 | VIN6 | input | Analog input channel 6, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 5 | VIN7 | input | Analog input channel 7, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 6 | GND1 | power_in | Ground reference for the internal reference circuitry and all analog inputs; must be within 0.3 V of GND and connected to the system GND plane, with VREF decoupled to it by 10 μF. |
| 7 | VREF | power_in | Internal 2.5 V reference output, which can be buffered and used externally, or disabled and driven by an external reference of 2.0 V to 2.5 V; decouple with 10 μF to GND1. |
| 8 | DCAP | passive | Decoupling capacitor pin for the internal LDO, requiring 1 μF recommended capacitors to GND. |
| 9 | GND | power_in | Ground reference for all analog and digital circuitry, which must be within 0.3 V of GND1 and connected to the system ground plane. |
| 10 | VDD | power_in | Main supply voltage of 2.8 V to 3.6 V, to be decoupled to GND with 10 μF and 100 nF capacitors. |
| 11 | CS | input | Active-low chip select; the falling edge starts a conversion and frames the serial transfer, with DOUT enabled while CS is low. |
| 12 | TSENSE_BUSY | output | Busy output that goes high when a temperature sensor conversion starts and stays high until it completes. |
| 13 | DIN | input | Serial data input for writing the control register, clocked in on the falling edge of SCLK. |
| 14 | DOUT | output | Serial data output carrying four channel address bits followed by 12 bits of MSB-first conversion data, clocked out on the falling edge of SCLK. |
| 15 | SCLK | input | Serial clock input for accessing conversion data from the AD7298 (fSCLK up to 20 MHz per Table 1 conditions). |
| 16 | VDRIVE | power_in | Logic supply that sets the digital interface voltage; range 1.65 V to 3.6 V, may be lower than VDD but must not exceed VDD by more than 0.3 V, and should be decoupled to GND. |
| 17 | PD/RST | input | Power-down pin that places the part in full power-down when held low beyond 100 ns, and resets the device when pulsed low for 1 ns to 100 ns; analog inputs must be at 0 V before power-down. |
| 18 | VIN0 | input | Analog input channel 0, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 19 | VIN1 | input | Analog input channel 1, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 20 | VIN2 | input | Analog input channel 2, single-ended, accepts 0 V to 2.5 V; unused inputs should be connected to GND1. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-20(4x4) |
| Category | ADC/DAC/Data Conversion |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage | VDD | 2.8 | 3 | 3.6 | V |  | 4 |
| VDRIVE logic supply voltage | VDRIVE | 1.65 | 3 | 3.6 | V |  | 4 |
| Normal mode (operational) total supply current | ITOTAL |  | 5.8 | 6.3 | mA | VDD = 3.6 V, VDRIVE = 3.6 V | 4 |
| Normal mode (static) total supply current | ITOTAL |  | 4.1 | 4.6 | mA | VDD = 3.6 V, VDRIVE = 3.6 V | 4 |
| Partial power-down total supply current | ITOTAL |  | 2.7 | 3.3 | mA | VDD = 3.6 V, VDRIVE = 3.6 V | 4 |
| Full power-down total supply current | ITOTAL |  | 1 | 1.6 | μA | TA = −40°C to +25°C | 4 |
| Power dissipation, normal mode (operational) |  |  | 17.4 | 18.9 | mW | VDD = 3 V, VDRIVE = 3 V | 4 |
| Power dissipation, normal mode (static) |  |  | 14.8 | 16.6 | mW |  | 4 |
| Power dissipation, partial power-down mode |  |  | 9.8 | 11.9 | mW |  | 4 |
| Power dissipation, full power-down mode |  |  | 3.6 | 5.8 | μW | TA = −40°C to +25°C | 4 |
| Signal-to-noise ratio | SNR | 70 | 72 |  | dB | fIN = 50 kHz sine wave | 3 |
| Signal-to-noise and distortion ratio | SINAD | 70 | 71 |  | dB | fIN = 50 kHz sine wave | 3 |
| Total harmonic distortion | THD |  | -82 | -77 | dB | fIN = 50 kHz sine wave | 3 |
| Spurious-free dynamic range | SFDR |  | -84 | -77.5 | dB | fIN = 50 kHz sine wave | 3 |
| Integral nonlinearity | INL | -1 | 0.5 | 1 | LSB |  | 3 |
| Differential nonlinearity | DNL | -0.99 | 0.5 | 0.99 | LSB | Guaranteed no missed codes to 12 bits | 3 |
| Offset error |  | -4.5 | 2 | 4.5 | LSB |  | 3 |
| Offset error matching |  | -4.5 | 2.5 | 4.5 | LSB |  | 3 |
| Gain error |  | -4 | 1 | 4 | LSB |  | 3 |
| Gain error matching |  | -2.5 | 1 | 2.5 | LSB |  | 3 |
| Analog input DC leakage current |  | -1 | 0.01 | 1 | μA |  | 3 |
| Reference output voltage |  | 2.4925 | 2.5 | 2.5075 | V | ±0.3% maximum @ 25°C | 3 |
| Reference input voltage range |  | 1 |  | 2.5 | V |  | 3 |
| Reference DC leakage current |  | -1 | 0.01 | 1 | μA | External reference applied to Pin VREF | 3 |
| VREF temperature coefficient |  |  | 12 | 35 | ppm/°C |  | 3 |
| Logic input current | IIN | -1 | 0.01 | 1 | μA | VIN = 0 V or VDRIVE | 4 |
| Floating state leakage current |  | -1 | 0.01 | 1 | μA |  | 4 |
| Internal temperature sensor accuracy |  | -2 | 1 | 2 | °C | TA = −40°C to +85°C | 4 |
| Internal temperature sensor accuracy |  | -3 | 1 | 3 | °C | TA = +85°C to +125°C | 4 |
| Internal temperature sensor operating range |  | -40 |  | 125 | °C |  | 4 |
| Conversion time, temperature sensor channel | tCONVERT |  |  | 100 | μs | Temperature sensor channel | 5 |
| Frequency of external serial clock (minimum) | fSCLK | 50 |  |  | kHz | Frequency of external serial clock | 5 |
| Frequency of external serial clock (maximum) | fSCLK |  |  | 20 | MHz | Frequency of external serial clock | 5 |
| Quiet time between end of serial read and start of next conversion | tQUIET | 6 |  |  | ns | Repeat and nonrepeat mode | 5 |
| CS to SCLK setup time | t2 | 10 |  |  | ns |  | 5 |
| Delay from CS falling edge until DOUT three-state disabled | t3 |  |  | 15 | ns |  | 5 |
| Data access time after SCLK falling edge | t4 |  |  | 35 | ns | VDRIVE = 1.65 V to 3 V | 5 |
| Data access time after SCLK falling edge | t4 |  |  | 28 | ns | VDRIVE = 3 V to 3.6 V | 5 |
| SCLK to DOUT valid hold time | t7 | 14 |  |  | ns |  | 5 |
| SCLK falling edge to DOUT high impedance | t8 | 16 |  | 34 | ns |  | 5 |
| DIN setup time prior to SCLK falling edge | t9 | 5 |  |  | ns |  | 5 |
| DIN hold time after SCLK falling edge | t10 | 4 |  |  | ns |  | 5 |
| TSENSE_BUSY falling edge to CS falling edge | t11 | 100 |  |  | ns |  | 5 |
| Delay from CS rising edge to DOUT high impedance | t12 |  |  | 30 | ns |  | 5 |
| Internal reference power-up time from full power-down | tPOWER-UP |  |  | 6 | ms |  | 5 |
| VDD to GND | VDD | -0.3 |  | 5 | V |  | 6 |
| VDRIVE to GND | VDRIVE | -0.3 |  | 5 | V |  | 6 |
| Analog input voltage to GND1 |  | -0.3 |  | 3 | V |  | 6 |
| VREF to GND1 | VREF | -0.3 |  | 3 | V |  | 6 |
| GND1 to GND |  | -0.3 |  | 0.3 | V |  | 6 |
| Input current to any pin except supplies |  | -10 |  | 10 | mA |  | 6 |
| Operating temperature range |  | -40 |  | 125 | °C |  | 6 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 6 |
| Junction temperature |  |  |  | 150 | °C |  | 6 |
| Pb-free soldering reflow temperature |  |  |  | 260 | °C |  | 6 |
| Thermal resistance, junction-to-ambient | θJA |  | 52 |  | °C/W | 20-Lead LFCSP | 6 |
| Thermal resistance, junction-to-case | θJC |  | 6.5 |  | °C/W | 20-Lead LFCSP | 6 |

## CAD (KiCad official)

- Symbol: `AD7298BCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
- 3D model files: `ad7298bcpz-rl7-etched.step` / `ad7298bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7298bcpz-rl7.step` / `ad7298bcpz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7298.pdf) (24 pp, sha256 `aa6164eb83a61130`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7298bcpz-rl7-datasheet.pdf)

AD7298BCPZ-RL7

Verified AD7298BCPZ-RL7

Verification log 1 record

AD7298BCPZ-RL7

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance