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AD7265BCPZ

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad7265bcpzfactory-2.0.0extractor-text

Verified AD7265BCPZ

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7265BCPZ · LFCSP-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 27-page datasheet
  • ✓distributor: lcsc C578407, digikey 505-AD7265BCPZ-ND, mouser 584-AD7265BCPZ
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-2gttbt1c/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.27)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7265bcpz.kicad_sym✓ ad7265bcpz.kicad_mod✓ ad7265bcpz.step
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Contents

README

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AD7265BCPZ

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-32(5x5)

AD7265BCPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Digital ground reference for all digital circuitry; both DGND pins should connect to the system DGND plane and must not be more than 0.3 V from AGND, even transiently.
2 REF SELECT input Logic input where tying it to DGND selects the on-chip 2.5 V reference for both ADCs, and a logic high lets an external reference be applied through DCAPA and/or DCAPB.
3 AVDD power_in Analog supply voltage of 2.7 V to 5.25 V, the only supply for all analog circuitry, which must stay within 0.3 V of DVDD even transiently and be decoupled to AGND.
4 DCAPA passive Decoupling capacitor pin for the ADC A reference buffer, where 470 nF is recommended, and it can also accept an external reference when REF SELECT is high.
5 AGND power_in Analog ground reference for all analog circuitry and analog input signals, which should connect to the system AGND plane and not be more than 0.3 V from DGND.
6 AGND power_in Analog ground reference for all analog circuitry, which should connect to the system AGND plane and not be more than 0.3 V from DGND.
7 VA1 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
8 VA2 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
9 VA3 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
10 VA4 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
11 VA5 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
12 VA6 passive Analog input of ADC A, programmable as one of six single-ended channels or as part of three true differential pairs.
13 VB6 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
14 VB5 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
15 VB4 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
16 VB3 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
17 VB2 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
18 VB1 passive Analog input of ADC B, programmable as one of six single-ended channels or as part of three true differential pairs.
19 AGND power_in Analog ground reference for all analog circuitry, which should connect to the system AGND plane and not be more than 0.3 V from DGND.
20 DCAPB passive Decoupling capacitor pin for the ADC B reference buffer, where 470 nF is recommended, and it can also accept an external reference when REF SELECT is high.
21 RANGE input Logic input setting the analog input range, where a logic low gives 0 V to VREF and a logic high when CS goes low gives 2 × VREF.
22 SGL/DIFF input Logic input selecting differential pairs when low and single-ended operation when high.
23 A2 input Multiplexer select logic input that chooses the channel pair converted simultaneously and must be set before the acquisition time and the falling edge of CS.
24 A1 input Multiplexer select logic input that chooses the channel pair converted simultaneously and must be set before the acquisition time and the falling edge of CS.
25 A0 input Multiplexer select logic input that chooses the channel pair converted simultaneously and must be set before the acquisition time and the falling edge of CS.
26 CS input Active-low chip select that initiates conversions on its falling edge and frames the serial data transfer.
27 SCLK input Serial clock logic input that clocks out the conversion data and also serves as the conversion clock source.
28 DOUTB output Serial data output for ADC B, with bits clocked out on the falling edge of SCLK, where 14 SCLKs access the data MSB first.
29 DGND power_in Digital ground reference for all digital circuitry, which should connect to the system DGND plane and not be more than 0.3 V from AGND, even transiently.
30 DOUTA output Serial data output for ADC A, carrying the same serial data stream as DOUTB, MSB first, with bits clocked out on the falling edge of SCLK.
31 VDRIVE power_in Logic supply that sets the interface voltage, which should be decoupled to DGND and must not exceed AVDD or DVDD by more than 0.3 V.
32 DVDD power_in Digital supply voltage of 2.7 V to 5.25 V for all digital circuitry, which must stay within 0.3 V of AVDD even transiently and be decoupled to DGND.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category ADC/DAC/Data Conversion
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-Noise Ratio (SNR) 71 dB fIN = 50 kHz sine wave; differential mode 3
Signal-to-Noise Ratio (SNR) 69 dB fIN = 50 kHz sine wave; single-ended and pseudo differential modes 3
Signal-to-Noise + Distortion Ratio (SINAD) 70 dB fIN = 50 kHz sine wave; differential mode 3
Signal-to-Noise + Distortion Ratio (SINAD) 68 dB fIN = 50 kHz sine wave; single-ended and pseudo differential modes 3
Total Harmonic Distortion (THD) -77 dB fIN = 50 kHz sine wave; differential mode 3
Total Harmonic Distortion (THD) -73 dB fIN = 50 kHz sine wave; single-ended and pseudo differential modes 3
Spurious-Free Dynamic Range (SFDR) -75 dB fIN = 50 kHz sine wave 3
Integral Nonlinearity -1 0.5 1 LSB differential mode 3
Integral Nonlinearity -1.5 0.5 1.5 LSB single-ended and pseudo differential modes 3
Differential Nonlinearity -0.99 0.99 LSB differential mode 3
Differential Nonlinearity -0.99 1.5 LSB single-ended and pseudo differential modes 3
Offset Error -6 6 LSB straight binary output coding 3
Gain Error -2.5 2.5 LSB straight binary output coding 3
Positive Gain Error -2 2 LSB twos complement output coding 3
Zero Code Error -5 5 LSB twos complement output coding 3
Negative Gain Error -2 2 LSB twos complement output coding 3
Reference Output Voltage 2.5 2.5 V ±0.2% max at 25°C 4
Reference Temperature Coefficient 10 20 ppm/°C 4
Input High Voltage VINH 2.8 V 4
Input Low Voltage VINL 0.4 V 4
Output Low Voltage VOL 0.4 V 4
Track-and-Hold Acquisition Time 90 ns Full-scale step input; VDD = 5 V 4
Track-and-Hold Acquisition Time 110 ns Full-scale step input; VDD = 3 V 4
Throughput Rate 1 MSPS 4
VDD VDD 2.7 5.25 V 4
VDRIVE VDRIVE 2.7 5.25 V 4
Normal Mode (Static) supply current IDD 2.3 mA Digital I/Ps = 0 V or VDRIVE; VDD = 5.25 V 4
Operational supply current IDD 3.5 4 mA fS = 1 MSPS; VDD = 5.25 V 4
Operational supply current IDD 2.7 3.2 mA fS = 1 MSPS; VDD = 3.6 V 4
Partial Power-Down Mode supply current IDD 500 µA Static 4
Full Power-Down Mode (VDD) supply current IDD 1 µA TA = −40°C to +85°C 4
Full Power-Down Mode (VDD) supply current IDD 2.8 µA TA > 85°C to 125°C 4
Power Dissipation Normal Mode (Operational) 21 mW VDD = 5.25 V 4
DC Leakage Current (analog input) -1 1 µA 4
DC Leakage Current (external reference) -2 2 µA External reference applied to Pin DCAPA/Pin DCAPB 4
Serial clock frequency fSCLK fSCLK 1 MHz TA = −40°C to +85°C 5
Serial clock frequency fSCLK fSCLK 4 MHz TA > 85°C to 125°C 5
Serial clock frequency fSCLK fSCLK 16 MHz 5
tQUIET tQUIET 30 ns Minimum time between end of serial read and next falling edge of CS 5
CS to SCLK setup time t2 t2 15 ns VDD = 5 V; TA = −40°C to +85°C 5
CS to SCLK setup time t2 t2 20 ns VDD = 3 V; TA = −40°C to +85°C 5
Delay from CS until DOUTA and DOUTB three-state disabled t3 t3 15 ns 5
Data access time after SCLK falling edge t4 t4 27 ns VDD = 5 V 5
Data access time after SCLK falling edge t4 t4 36 ns VDD = 3 V 5
SCLK to data valid hold time t7 t7 5 ns VDD = 5 V 5
SCLK to data valid hold time t7 t7 10 ns VDD = 3 V 5
CS rising edge to DOUTA, DOUTB high impedance t8 t8 15 ns 5
CS rising edge to falling edge pulse width t9 t9 30 ns 5
SCLK falling edge to DOUTA, DOUTB high impedance t10 t10 5 ns 5
SCLK falling edge to DOUTA, DOUTB high impedance t10 t10 50 ns 5
VDD to AGND VDD -0.3 7 V 6
DVDD to DGND DVDD -0.3 7 V 6
AVDD to DVDD -0.3 0.3 V 6
AGND to DGND -0.3 0.3 V 6
Digital Input Voltage to DGND -0.3 7 V 6
Input Current to Any Pin Except Supplies -10 10 mA 6
Operating Temperature Range TA -40 125 °C 6
Storage Temperature Range -65 150 °C 6
θJA Thermal Impedance θJA 108.2 °C/W LFCSP 6
θJC Thermal Impedance θJC 32.71 °C/W LFCSP 6

CAD (KiCad official)

  • Symbol: AD7265BCPZ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad7265bcpz-etched.step / ad7265bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7265bcpz.step / ad7265bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (27 pp, sha256 857cb1677ea06db5, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF