AD7195BCPZ-RL7

Analog Devices · Analog To Digital Converters (ADC) · QFN-32-EP(5x5)

AD7195BCPZ-RL7 from Analog Devices, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ACX2	output	Digital output for AC-excitation bridge switching; it is the inverse of ACX1 and is held low when the ACX bit is 0, with a non-overlap of 1/f(MCLK), which is 200 ns with a 4.92 MHz clock.
2	ACX2	output	Complement of the ACX2 output for AC-excitation bridge switching; it is held high when the ACX bit is 0.
3	ACX1	output	Digital output for AC-excitation bridge polarity control; high means normal excitation and low means reversed (chopped) excitation, and it is held high when the ACX bit is 0.
4	ACX1	output	Complement of the ACX1 output for AC-excitation bridge switching; it is held low when the ACX bit is 0.
5	AVDD	power_in	Analog supply voltage, 4.75 V to 5.25 V, independent of DVDD.
6	AGND	power_in	Analog reference ground point.
7	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
8	AINCOM	passive	Reference input to which AIN1 to AIN4 are referenced when the part is configured for pseudo-differential operation.
9	AIN1	passive	Analog input that acts as the positive input of a fully differential pair with AIN2, or as a pseudo-differential input referenced to AINCOM.
10	AIN2	passive	Analog input that acts as the negative input of a fully differential pair with AIN1, or as a pseudo-differential input referenced to AINCOM.
11	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
12	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
13	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
14	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
15	AIN3	passive	Analog input that acts as the positive input of a fully differential pair with AIN4, or as a pseudo-differential input referenced to AINCOM.
16	AIN4	passive	Analog input that acts as the negative input of a fully differential pair with AIN3, or as a pseudo-differential input referenced to AINCOM.
17	REFIN(+)	passive	Positive reference input that may be placed between AVDD and AGND + 1 V, with a nominal reference (REFIN(+) minus REFIN(-)) of AVDD and operation from 1 V to AVDD.
18	REFIN(-)	passive	Negative reference input that may be any value between AGND and AVDD - 1 V.
19	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
20	BPDSW	passive	Bridge power-down switch to AGND; it can sink 30 mA continuously with a maximum on-resistance of 10 Ω.
21	AGND	power_in	Analog reference ground point.
22	DGND	power_in	Digital ground reference point.
23	AVDD	power_in	Analog supply voltage, 4.75 V to 5.25 V, independent of DVDD.
24	DVDD	power_in	Digital supply voltage, 2.7 V to 5.25 V, independent of AVDD.
25	SYNC	input	Logic input for synchronizing the digital filter with the analog modulator; driving it low resets the filter and holds the modulator in reset, and it has an internal pull-up to DVDD.
26	NC	unconnected	No connect; the datasheet states this pin should be connected to AGND.
27	DOUT/RDY	output	Serial data output and data-ready output; it goes low when a conversion is complete and returns high when the data is read or before a new update.
28	DIN	input	Serial data input to the ADC input shift register, which loads the communications register.
29	MCLK1	passive	Connects to MCLK2 for an external crystal; it is left unconnected when a CMOS clock drives MCLK2.
30	MCLK2	bidirectional	Master clock pin that can output the 4.92 MHz internal clock, or accept a crystal (between MCLK1 and MCLK2) or a CMOS-compatible external clock.
31	SCLK	input	Serial clock input with a Schmitt-trigger input that is suitable for opto-isolated applications.
32	CS	input	Active-low chip select input for selecting the ADC; it can be hard-wired low for 3-wire operation.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	QFN-32-EP(5x5)
Category	Data Acquisition
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output data rate, Sinc4 filter, chop disabled		4.7		4800	Hz	斩波禁用	3
Output data rate, Sinc4 filter, chop enabled		1.17		1200	Hz	斩波使能，Sinc4滤波器	3
Output data rate, Sinc3 filter, chop enabled		1.56		1600	Hz	斩波使能，Sinc3滤波器	3
Offset error		-5	1	5	µV	模拟输入配置为差分模式	3
Offset error drift vs temperature		-5		5	nV/°C		3
Gain drift vs temperature		-1		1	ppm/°C		3
Internal temperature sensor accuracy		-2		2	°C	单点校准之后，典型值	4
Internal clock tolerance		-4		4	%	4.92 MHz内部时钟	32
Analog supply voltage AVDD (AVDD − AGND)	AVDD	4.75		5.25	V		5
Digital supply voltage DVDD (DVDD − DGND)	DVDD	2.7		5.25	V		5
AIDD supply current	AIDD		0.85	1	mA	增益 = 1，缓冲关	5
AIDD supply current	AIDD		1.1	1.3	mA	增益 = 1，缓冲开	5
AIDD supply current	AIDD		3.5	4.5	mA	增益 = 8，缓冲关	5
AIDD supply current	AIDD		4	5	mA	增益 = 8，缓冲开	5
AIDD supply current	AIDD		5	6.4	mA	增益 = 16至128，缓冲关	5
AIDD supply current	AIDD		5.5	6.9	mA	增益 = 16至128，缓冲开	5
DIDD supply current	DIDD		0.35	0.4	mA	DVDD = 3 V	5
DIDD supply current	DIDD		0.5	0.6	mA	DVDD = 5 V	5
Power-down supply current IDD(power-down)	IDD			2	µA	省电模式	5
Logic input high voltage	VINH	2.5			V	DVDD = 3 V	4
Logic input high voltage	VINH	3.5			V	DVDD = 5 V	4
Logic input low voltage	VINL			0.4	V	DVDD = 3 V	4
Logic input low voltage	VINL			0.8	V	DVDD = 5 V	4
Logic input current		-10		10	µA		5
Logic input hysteresis			0.1	0.25	V		5
DOUT/RDY output high voltage	VOH	4			V	DVDD = 5 V, ISOURCE = 200 µA	5
DOUT/RDY output low voltage	VOL			0.4	V	DVDD = 3 V, ISINK = 100 µA	5
DOUT/RDY floating-state leakage current		-10		10	µA		5
ACX digital output high voltage	VOH	4			V	AVDD = 5 V, ISOURCE = 200 µA	4
ACX digital output low voltage	VOL			0.4	V	AVDD = 5 V, ISINK = 800 µA	4
Internal clock frequency		4.72		5.12	MHz	内部时钟	4
External clock / crystal frequency		2.4576	4.9152	5.12	MHz	外部时钟/晶振	4
Analog input absolute voltage limit (unbuffered)		-0.05			V	无缓冲模式，相对AGND；上限为AVDD + 0.05 V（未给出数值）	4
Analog input absolute voltage limit (buffered)		0.25			V	缓冲模式，相对AGND；上限为AVDD − 0.25 V（未给出数值）	4
Analog input current (buffered)		-2		2	nA	缓冲模式	4
Analog input current (unbuffered)		-4.5		4.5	nA	无缓冲模式	4
Absolute REFIN voltage limit		-0.05			V	相对GND；上限为AVDD + 0.05 V（未给出数值）	4
REFIN reference detect level		0.3		0.6	V	REFIN(+) − REFIN(−)	4
Bridge power-down switch on-resistance	RON			10	Ω	BPDSW	4
Bridge power-down switch allowable continuous current				30	mA	BPDSW	4
Excitation current (AIN)			500		nA	激励电流 AIN current	4
Absolute max AVDD to AGND	AVDD	-0.3		6.5	V	TA = 25°C	8
Absolute max DVDD to AGND	DVDD	-0.3		6.5	V	TA = 25°C	8
Absolute max AGND to DGND		-0.3		0.3	V	TA = 25°C	8
Absolute max analog input voltage to AGND		-0.3			V	TA = 25°C；上限为AVDD + 0.3 V（未给出数值）	8
Absolute max REFIN voltage to AGND		-0.3			V	TA = 25°C；上限为AVDD + 0.3 V（未给出数值）	8
Absolute max digital input voltage to DGND		-0.3			V	TA = 25°C；上限为DVDD + 0.3 V（未给出数值）	8
Absolute max digital output voltage to DGND		-0.3			V	TA = 25°C；上限为DVDD + 0.3 V（未给出数值）	8
Absolute max AIN/digital input current				10	mA	TA = 25°C	8
Operating temperature range	TA	-40		105	°C		8
Storage temperature range		-65		150	°C		8
Maximum junction temperature	TJ			150	°C		8
Pin temperature, reflow				260	°C	回流焊	8
Recommended AVDD	AVDD	4.75		5.25	V		3
Recommended DVDD	DVDD	2.7		5.25	V		3
Thermal resistance junction-to-ambient	θJA		32.5		°C/W	32引脚LFCSP_WQ，焊接在电路板上，最差条件	8
Thermal resistance junction-to-case	θJC		32.71		°C/W	32引脚LFCSP_WQ	8
Sensitivity of temperature sensor			2815		Codes/°C		4
SCLK/clock duty cycle (internal clock)			50		%	内部时钟占空比 50:50	4

CAD (KiCad official)

Symbol: AD7195BCPZ-RL7
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: ad7195bcpz-rl7-etched.step / ad7195bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7195bcpz-rl7.step / ad7195bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (44 pp, sha256 e20cba998a761a41, retrieved 2026-10-18, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7195BCPZ-RL7

**Analog Devices** · Analog To Digital Converters (ADC) · QFN-32-EP(5x5)

AD7195BCPZ-RL7 from Analog Devices, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ACX2 | output | Digital output for AC-excitation bridge switching; it is the inverse of ACX1 and is held low when the ACX bit is 0, with a non-overlap of 1/f(MCLK), which is 200 ns with a 4.92 MHz clock. |
| 2 | ACX2 | output | Complement of the ACX2 output for AC-excitation bridge switching; it is held high when the ACX bit is 0. |
| 3 | ACX1 | output | Digital output for AC-excitation bridge polarity control; high means normal excitation and low means reversed (chopped) excitation, and it is held high when the ACX bit is 0. |
| 4 | ACX1 | output | Complement of the ACX1 output for AC-excitation bridge switching; it is held low when the ACX bit is 0. |
| 5 | AVDD | power_in | Analog supply voltage, 4.75 V to 5.25 V, independent of DVDD. |
| 6 | AGND | power_in | Analog reference ground point. |
| 7 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 8 | AINCOM | passive | Reference input to which AIN1 to AIN4 are referenced when the part is configured for pseudo-differential operation. |
| 9 | AIN1 | passive | Analog input that acts as the positive input of a fully differential pair with AIN2, or as a pseudo-differential input referenced to AINCOM. |
| 10 | AIN2 | passive | Analog input that acts as the negative input of a fully differential pair with AIN1, or as a pseudo-differential input referenced to AINCOM. |
| 11 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 12 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 13 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 14 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 15 | AIN3 | passive | Analog input that acts as the positive input of a fully differential pair with AIN4, or as a pseudo-differential input referenced to AINCOM. |
| 16 | AIN4 | passive | Analog input that acts as the negative input of a fully differential pair with AIN3, or as a pseudo-differential input referenced to AINCOM. |
| 17 | REFIN(+) | passive | Positive reference input that may be placed between AVDD and AGND + 1 V, with a nominal reference (REFIN(+) minus REFIN(-)) of AVDD and operation from 1 V to AVDD. |
| 18 | REFIN(-) | passive | Negative reference input that may be any value between AGND and AVDD - 1 V. |
| 19 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 20 | BPDSW | passive | Bridge power-down switch to AGND; it can sink 30 mA continuously with a maximum on-resistance of 10 Ω. |
| 21 | AGND | power_in | Analog reference ground point. |
| 22 | DGND | power_in | Digital ground reference point. |
| 23 | AVDD | power_in | Analog supply voltage, 4.75 V to 5.25 V, independent of DVDD. |
| 24 | DVDD | power_in | Digital supply voltage, 2.7 V to 5.25 V, independent of AVDD. |
| 25 | SYNC | input | Logic input for synchronizing the digital filter with the analog modulator; driving it low resets the filter and holds the modulator in reset, and it has an internal pull-up to DVDD. |
| 26 | NC | unconnected | No connect; the datasheet states this pin should be connected to AGND. |
| 27 | DOUT/RDY | output | Serial data output and data-ready output; it goes low when a conversion is complete and returns high when the data is read or before a new update. |
| 28 | DIN | input | Serial data input to the ADC input shift register, which loads the communications register. |
| 29 | MCLK1 | passive | Connects to MCLK2 for an external crystal; it is left unconnected when a CMOS clock drives MCLK2. |
| 30 | MCLK2 | bidirectional | Master clock pin that can output the 4.92 MHz internal clock, or accept a crystal (between MCLK1 and MCLK2) or a CMOS-compatible external clock. |
| 31 | SCLK | input | Serial clock input with a Schmitt-trigger input that is suitable for opto-isolated applications. |
| 32 | CS | input | Active-low chip select input for selecting the ADC; it can be hard-wired low for 3-wire operation. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | QFN-32-EP(5x5) |
| Category | Data Acquisition |
| Pins | 33 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output data rate, Sinc4 filter, chop disabled |  | 4.7 |  | 4800 | Hz | 斩波禁用 | 3 |
| Output data rate, Sinc4 filter, chop enabled |  | 1.17 |  | 1200 | Hz | 斩波使能，Sinc4滤波器 | 3 |
| Output data rate, Sinc3 filter, chop enabled |  | 1.56 |  | 1600 | Hz | 斩波使能，Sinc3滤波器 | 3 |
| Offset error |  | -5 | 1 | 5 | µV | 模拟输入配置为差分模式 | 3 |
| Offset error drift vs temperature |  | -5 |  | 5 | nV/°C |  | 3 |
| Gain drift vs temperature |  | -1 |  | 1 | ppm/°C |  | 3 |
| Internal temperature sensor accuracy |  | -2 |  | 2 | °C | 单点校准之后，典型值 | 4 |
| Internal clock tolerance |  | -4 |  | 4 | % | 4.92 MHz内部时钟 | 32 |
| Analog supply voltage AVDD (AVDD − AGND) | AVDD | 4.75 |  | 5.25 | V |  | 5 |
| Digital supply voltage DVDD (DVDD − DGND) | DVDD | 2.7 |  | 5.25 | V |  | 5 |
| AIDD supply current | AIDD |  | 0.85 | 1 | mA | 增益 = 1，缓冲关 | 5 |
| AIDD supply current | AIDD |  | 1.1 | 1.3 | mA | 增益 = 1，缓冲开 | 5 |
| AIDD supply current | AIDD |  | 3.5 | 4.5 | mA | 增益 = 8，缓冲关 | 5 |
| AIDD supply current | AIDD |  | 4 | 5 | mA | 增益 = 8，缓冲开 | 5 |
| AIDD supply current | AIDD |  | 5 | 6.4 | mA | 增益 = 16至128，缓冲关 | 5 |
| AIDD supply current | AIDD |  | 5.5 | 6.9 | mA | 增益 = 16至128，缓冲开 | 5 |
| DIDD supply current | DIDD |  | 0.35 | 0.4 | mA | DVDD = 3 V | 5 |
| DIDD supply current | DIDD |  | 0.5 | 0.6 | mA | DVDD = 5 V | 5 |
| Power-down supply current IDD(power-down) | IDD |  |  | 2 | µA | 省电模式 | 5 |
| Logic input high voltage | VINH | 2.5 |  |  | V | DVDD = 3 V | 4 |
| Logic input high voltage | VINH | 3.5 |  |  | V | DVDD = 5 V | 4 |
| Logic input low voltage | VINL |  |  | 0.4 | V | DVDD = 3 V | 4 |
| Logic input low voltage | VINL |  |  | 0.8 | V | DVDD = 5 V | 4 |
| Logic input current |  | -10 |  | 10 | µA |  | 5 |
| Logic input hysteresis |  |  | 0.1 | 0.25 | V |  | 5 |
| DOUT/RDY output high voltage | VOH | 4 |  |  | V | DVDD = 5 V, ISOURCE = 200 µA | 5 |
| DOUT/RDY output low voltage | VOL |  |  | 0.4 | V | DVDD = 3 V, ISINK = 100 µA | 5 |
| DOUT/RDY floating-state leakage current |  | -10 |  | 10 | µA |  | 5 |
| ACX digital output high voltage | VOH | 4 |  |  | V | AVDD = 5 V, ISOURCE = 200 µA | 4 |
| ACX digital output low voltage | VOL |  |  | 0.4 | V | AVDD = 5 V, ISINK = 800 µA | 4 |
| Internal clock frequency |  | 4.72 |  | 5.12 | MHz | 内部时钟 | 4 |
| External clock / crystal frequency |  | 2.4576 | 4.9152 | 5.12 | MHz | 外部时钟/晶振 | 4 |
| Analog input absolute voltage limit (unbuffered) |  | -0.05 |  |  | V | 无缓冲模式，相对AGND；上限为AVDD + 0.05 V（未给出数值） | 4 |
| Analog input absolute voltage limit (buffered) |  | 0.25 |  |  | V | 缓冲模式，相对AGND；上限为AVDD − 0.25 V（未给出数值） | 4 |
| Analog input current (buffered) |  | -2 |  | 2 | nA | 缓冲模式 | 4 |
| Analog input current (unbuffered) |  | -4.5 |  | 4.5 | nA | 无缓冲模式 | 4 |
| Absolute REFIN voltage limit |  | -0.05 |  |  | V | 相对GND；上限为AVDD + 0.05 V（未给出数值） | 4 |
| REFIN reference detect level |  | 0.3 |  | 0.6 | V | REFIN(+) − REFIN(−) | 4 |
| Bridge power-down switch on-resistance | RON |  |  | 10 | Ω | BPDSW | 4 |
| Bridge power-down switch allowable continuous current |  |  |  | 30 | mA | BPDSW | 4 |
| Excitation current (AIN) |  |  | 500 |  | nA | 激励电流 AIN current | 4 |
| Absolute max AVDD to AGND | AVDD | -0.3 |  | 6.5 | V | TA = 25°C | 8 |
| Absolute max DVDD to AGND | DVDD | -0.3 |  | 6.5 | V | TA = 25°C | 8 |
| Absolute max AGND to DGND |  | -0.3 |  | 0.3 | V | TA = 25°C | 8 |
| Absolute max analog input voltage to AGND |  | -0.3 |  |  | V | TA = 25°C；上限为AVDD + 0.3 V（未给出数值） | 8 |
| Absolute max REFIN voltage to AGND |  | -0.3 |  |  | V | TA = 25°C；上限为AVDD + 0.3 V（未给出数值） | 8 |
| Absolute max digital input voltage to DGND |  | -0.3 |  |  | V | TA = 25°C；上限为DVDD + 0.3 V（未给出数值） | 8 |
| Absolute max digital output voltage to DGND |  | -0.3 |  |  | V | TA = 25°C；上限为DVDD + 0.3 V（未给出数值） | 8 |
| Absolute max AIN/digital input current |  |  |  | 10 | mA | TA = 25°C | 8 |
| Operating temperature range | TA | -40 |  | 105 | °C |  | 8 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 8 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 8 |
| Pin temperature, reflow |  |  |  | 260 | °C | 回流焊 | 8 |
| Recommended AVDD | AVDD | 4.75 |  | 5.25 | V |  | 3 |
| Recommended DVDD | DVDD | 2.7 |  | 5.25 | V |  | 3 |
| Thermal resistance junction-to-ambient | θJA |  | 32.5 |  | °C/W | 32引脚LFCSP_WQ，焊接在电路板上，最差条件 | 8 |
| Thermal resistance junction-to-case | θJC |  | 32.71 |  | °C/W | 32引脚LFCSP_WQ | 8 |
| Sensitivity of temperature sensor |  |  | 2815 |  | Codes/°C |  | 4 |
| SCLK/clock duty cycle (internal clock) |  |  | 50 |  | % | 内部时钟占空比 50:50 | 4 |

## CAD (KiCad official)

- Symbol: `AD7195BCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `ad7195bcpz-rl7-etched.step` / `ad7195bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7195bcpz-rl7.step` / `ad7195bcpz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885974302527488) (44 pp, sha256 `e20cba998a761a41`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7195bcpz-rl7-datasheet.pdf)