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AD7194BCPZ

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AD7194BCPZ

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-32(5x5)

AD7194BCPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN1/P3 bidirectional Analog input AIN1 or, when GP32EN is set to 1, a general-purpose digital output referenced between AVDD and AGND.
2 AIN2/P2 bidirectional Analog input AIN2 or, when GP32EN is set to 1, a general-purpose digital output referenced between AVDD and AGND.
3 AIN3/P1/REFIN2(+) bidirectional Analog input AIN3, a general-purpose output when GP10EN is set to 1, or positive reference input REFIN2(+) when REFSEL is set to 1, which can lie between AVDD and AGND + 1 V.
4 AIN4/P0/REFIN2(-) bidirectional Analog input AIN4, a general-purpose output when GP10EN is set to 1, or negative reference input REFIN2(−) when REFSEL is set to 1, which can lie between AGND and AVDD − 1 V.
5 AINCOM input Common reference for AIN1 to AIN16 when the pseudo bit is set to 1.
6 AGND power_in Analog ground reference point.
7 AIN5 input Analog input pin.
8 AIN6 input Analog input pin.
9 AIN7 input Analog input pin.
10 AIN8 input Analog input pin.
11 AIN9 input Analog input pin.
12 AIN10 input Analog input pin.
13 AIN11 input Analog input pin.
14 AIN12 input Analog input pin.
15 AIN13 input Analog input pin.
16 AIN14 input Analog input pin.
17 REFIN1(+) input Positive reference input that can lie between AVDD and AGND + 1 V, with a nominal reference of AVDD and operation from 1 V to AVDD.
18 REFIN1(-) input Negative reference input that can lie between AGND and AVDD − 1 V.
19 AIN15 input Analog input pin.
20 AIN16 input Analog input pin.
21 AGND power_in Analog ground reference point.
22 DGND power_in Digital ground reference point.
23 AVDD power_in Analog supply voltage of 3 V to 5.25 V that is independent of DVDD.
24 DVDD power_in Digital supply voltage of 2.7 V to 5.25 V that is independent of AVDD.
25 SYNC input Logic input that synchronizes digital filters and modulators across multiple devices, resetting them while low, with an internal pull-up to DVDD.
26 NC unconnected No connect; do not connect to this pin.
27 DOUT/RDY output Serial data output from the output shift register that also goes low to flag conversion completion (data ready).
28 DIN input Serial data input to the input shift register that loads the control registers selected by the communications register.
29 MCLK1 passive Crystal connection to MCLK2 when the master clock is provided by an external crystal; left unconnected when MCLK2 is driven by a CMOS clock.
30 MCLK2 bidirectional Master clock pin that outputs the internal 4.92 MHz clock or accepts an external CMOS-compatible clock or crystal.
31 SCLK input Serial clock input with a Schmitt-triggered input for data transfers to and from the ADC.
32 CS input Active-low chip select that selects the ADC and may be hardwired low for 3-wire operation.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Converters
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Data Rate 4.7 4800 Hz Chop disabled 3
Output Data Rate 1.17 1200 Hz Chop enabled, sinc4 filter 3
Output Data Rate 1.56 1600 Hz Chop enabled, sinc3 filter 3
Integral Nonlinearity -10 10 ppm of FSR Gain = 1 (printed as Gain = 12), AVDD = 5 V 3
Integral Nonlinearity -15 15 ppm of FSR Gain = 1 (printed as Gain = 12), AVDD = 3 V 3
Integral Nonlinearity -30 30 ppm of FSR Gain > 1, AVDD = 5 V 3
Offset Error -1 1 µV Chop enabled, AVDD = 5 V 3
Offset Error -0.5 0.5 µV Chop enabled, AVDD = 3 V 3
Offset Error Drift vs. Temperature -5 5 nV/°C Gain = 32 to 128; chop disabled 3
Gain Error -0.001 0.001 % AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) 3
Gain Error -0.003 0.003 % Gain > 1, after internal full-scale calibration, AVDD ≥ 4.75 V 3
Gain Error -0.005 0.005 % Gain > 1, after internal full-scale calibration, AVDD < 4.75 V 3
Gain Error -0.4 % Gain = 128, before full-scale calibration (see Table 27) 3
Gain Drift vs. Temperature -1 1 ppm/°C 3
Power Supply Rejection 90 dB Gain = 1, VIN = 1 V 3
Power Supply Rejection 95 110 dB Gain > 1, VIN = 1 V/gain 3
Full-Scale Calibration Limit 1.05 × FS 6
Zero-Scale Calibration Limit -1.05 × FS 6
Input Span 0.8 2.1 × FS 6
AVDD − AGND AVDD 3 5.25 V 6
DVDD − DGND DVDD 2.7 5.25 V 6
AIDD Current AIDD 0.85 1.1 mA Gain = 1, buffer off 6
AIDD Current AIDD 1 1.35 mA Gain = 1, buffer on 6
AIDD Current AIDD 2.8 3.6 mA Gain = 8, buffer off 6
AIDD Current AIDD 3.2 3.85 mA Gain = 8, buffer on 6
AIDD Current AIDD 3.8 4.7 mA Gain = 16 to 128, buffer off 6
AIDD Current AIDD 4.3 5.3 mA Gain = 16 to 128, buffer on 6
DIDD Current DIDD 0.35 0.4 mA DVDD = 3 V 6
DIDD Current DIDD 0.5 0.6 mA DVDD = 5 V 6
DIDD Current DIDD 1.5 mA External crystal used 6
IDD IDD 3 µA Power-down mode 6
Internal Clock Tolerance -4 4 % Internal 4.92 MHz clock 36
AVDD to AGND AVDD -0.3 6.5 V TA = 25°C 9
DVDD to AGND DVDD -0.3 6.5 V TA = 25°C 9
AGND to DGND -0.3 0.3 V TA = 25°C 9
AINx/Digital Input Current 10 mA TA = 25°C 9
Operating Temperature Range -40 105 °C 9
Storage Temperature Range -65 150 °C 9
Maximum Junction Temperature 150 °C 9
Lead Temperature, Soldering Reflow 260 °C 9
Thermal Resistance θJA θJA 32.5 °C/W 32-lead LFCSP, device soldered in circuit board 9
Thermal Resistance θJC θJC 32.71 °C/W 32-lead LFCSP 9
SCLK high pulse width t3 100 ns B version 7
SCLK low pulse width t4 100 ns B version 7
CS falling edge to DOUT/RDY active time t1 0 60 ns DVDD = 4.75 V to 5.25 V 7
CS falling edge to DOUT/RDY active time t1 80 ns DVDD = 2.7 V to 3.6 V 7
SCLK active edge to data valid delay t2 0 60 ns DVDD = 4.75 V to 5.25 V 7
SCLK active edge to data valid delay t2 80 ns DVDD = 2.7 V to 3.6 V 7
Bus relinquish time after CS inactive edge t5 10 80 ns 7
SCLK inactive edge to CS inactive edge t6 0 ns 7
SCLK inactive edge to DOUT/RDY high t7 10 ns 7
CS falling edge to SCLK active edge setup time t8 0 ns 7
Data valid to SCLK edge setup time t9 30 ns 7
Data valid to SCLK edge hold time t10 25 ns 7
CS rising edge to SCLK edge hold time t11 0 ns 7
Reset recovery period 200 µs Before accessing on-chip registers after a reset 36

CAD (KiCad official)

  • Symbol: AD7194BCPZ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad7194bcpz-etched.step / ad7194bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7194bcpz.step / ad7194bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (54 pp, sha256 e1491195e9fffe08, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF