AD7192BRUZ

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  "slug": "ad7192bruz",
  "title": "AD7192BRUZ",
  "brief": "Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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  "component": {
    "mpn": "AD7192BRUZ",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-24",
    "pin_count": 24,
    "category": "Data Converters",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7192.pdf",
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      "lbr": "ad7192bruz.lbr"
    },
    "distributor_links": {
      "lcsc": "C578397",
      "digikey": "505-AD7192BRUZ-ND",
      "mouser": "584-AD7192BRUZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T20:11:11Z",
      "source": "Component Ocean /api/assign-pns",
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        "lifecycle": "Restricted Availability"
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    },
    "pins": [
      {
        "number": "1",
        "name": "MCLK1",
        "type": "passive",
        "description": "Crystal connection to MCLK2 for the master clock; left unconnected when MCLK2 is driven by an external CMOS-compatible clock."
      },
      {
        "number": "2",
        "name": "MCLK2",
        "type": "bidirectional",
        "description": "Master clock pin for the internal 4.92 MHz clock, which can be made available here, or accepts a CMOS-compatible external clock (with MCLK1 unconnected) or a crystal across MCLK1 and MCLK2."
      },
      {
        "number": "3",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with a Schmitt-triggered input for data transfers to and from the ADC, which can be continuous or non-continuous."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select for the ADC, which can be hardwired low for 3-wire operation or used as a frame synchronization signal."
      },
      {
        "number": "5",
        "name": "P3",
        "type": "output",
        "description": "General-purpose digital output bit referenced between AVDD and AGND."
      },
      {
        "number": "6",
        "name": "P2",
        "type": "output",
        "description": "General-purpose digital output bit referenced between AVDD and AGND."
      },
      {
        "number": "7",
        "name": "P1/REFIN2(+)",
        "type": "bidirectional",
        "description": "General-purpose digital output referenced between AVDD and AGND; when REFSEL = 1 it is the REFIN2(+) positive reference input, which can lie between AVDD and AGND + 1 V and functions with references from 1 V to AVDD."
      },
      {
        "number": "8",
        "name": "P0/REFIN2(-)",
        "type": "bidirectional",
        "description": "General-purpose digital output referenced between AVDD and AGND; when REFSEL = 1 it is the REFIN2(−) negative reference input, which can lie between AGND and AVDD − 1 V."
      },
      {
        "number": "9",
        "name": "NC",
        "type": "unconnected",
        "description": "No connect; the datasheet states this pin should be tied to AGND."
      },
      {
        "number": "10",
        "name": "AINCOM",
        "type": "passive",
        "description": "Common reference input to which analog inputs AIN1 to AIN4 are referenced when configured for pseudodifferential operation."
      },
      {
        "number": "11",
        "name": "AIN1",
        "type": "passive",
        "description": "Analog input that acts as the positive input of a fully differential pair with AIN2, or as a pseudodifferential input referenced to AINCOM."
      },
      {
        "number": "12",
        "name": "AIN2",
        "type": "passive",
        "description": "Analog input that acts as the negative input of a fully differential pair with AIN1, or as a pseudodifferential input referenced to AINCOM."
      },
      {
        "number": "13",
        "name": "AIN3",
        "type": "passive",
        "description": "Analog input that acts as the positive input of a fully differential pair with AIN4, or as a pseudodifferential input referenced to AINCOM."
      },
      {
        "number": "14",
        "name": "AIN4",
        "type": "passive",
        "description": "Analog input that acts as the negative input of a fully differential pair with AIN3, or as a pseudodifferential input referenced to AINCOM."
      },
      {
        "number": "15",
        "name": "REFIN1(+)",
        "type": "passive",
        "description": "Positive external reference input, which can lie between AVDD and AGND + 1 V; the part functions with a reference from 1 V to AVDD."
      },
      {
        "number": "16",
        "name": "REFIN1(-)",
        "type": "passive",
        "description": "Negative reference input, which can lie anywhere between AGND and AVDD − 1 V."
      },
      {
        "number": "17",
        "name": "BPDSW",
        "type": "passive",
        "description": "Bridge power-down switch to AGND."
      },
      {
        "number": "18",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground reference point."
      },
      {
        "number": "19",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference point."
      },
      {
        "number": "20",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage, 3 V to 5.25 V, independent of DVDD."
      },
      {
        "number": "21",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital supply voltage, 2.7 V to 5.25 V, independent of AVDD."
      },
      {
        "number": "22",
        "name": "SYNC",
        "type": "input",
        "description": "Logic input for synchronizing digital filters and analog modulators across multiple devices; it has an internal pull-up to DVDD and resets RDY high when low."
      },
      {
        "number": "23",
        "name": "DOUT/RDY",
        "type": "output",
        "description": "Serial data output and data-ready output that goes low to indicate conversion completion; with CS low, data is placed on the SCLK falling edge and is valid on the SCLK rising edge."
      },
      {
        "number": "24",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to the ADC input shift register, with register selection set by the communications register bits."
      }
    ],
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        "guard_notes": [
          "extractor flagged: The datasheet's ordering guide lists AD7192BRUZ as 24-Lead TSSOP RU-24, so the 24-pin TSSOP pinout a; Pin types are judgment calls. MCLK1/MCLK2 can be a crystal, an output, or a clock input; P1/REFIN2(+; NC is marked unconnected in ERC terms, but the datasheet says it should be tied to AGND, which the d"
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        "at": "2026-10-28T20:10:56"
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      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-24",
      "Category": "Data Converters",
      "Pins": "24"
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        {
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