component

AD7192BRUZ

Public Made by Adom

by adom

Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad7192bruzfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ad7192bruz / README.md
History Download
Ray Publish 0.1.0 c7da74a 5d ago

AD7192BRUZ

Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24

AD7192BRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLK1 passive Crystal connection to MCLK2 for the master clock; left unconnected when MCLK2 is driven by an external CMOS-compatible clock.
2 MCLK2 bidirectional Master clock pin for the internal 4.92 MHz clock, which can be made available here, or accepts a CMOS-compatible external clock (with MCLK1 unconnected) or a crystal across MCLK1 and MCLK2.
3 SCLK input Serial clock input with a Schmitt-triggered input for data transfers to and from the ADC, which can be continuous or non-continuous.
4 CS input Active-low chip select for the ADC, which can be hardwired low for 3-wire operation or used as a frame synchronization signal.
5 P3 output General-purpose digital output bit referenced between AVDD and AGND.
6 P2 output General-purpose digital output bit referenced between AVDD and AGND.
7 P1/REFIN2(+) bidirectional General-purpose digital output referenced between AVDD and AGND; when REFSEL = 1 it is the REFIN2(+) positive reference input, which can lie between AVDD and AGND + 1 V and functions with references from 1 V to AVDD.
8 P0/REFIN2(-) bidirectional General-purpose digital output referenced between AVDD and AGND; when REFSEL = 1 it is the REFIN2(−) negative reference input, which can lie between AGND and AVDD − 1 V.
9 NC unconnected No connect; the datasheet states this pin should be tied to AGND.
10 AINCOM passive Common reference input to which analog inputs AIN1 to AIN4 are referenced when configured for pseudodifferential operation.
11 AIN1 passive Analog input that acts as the positive input of a fully differential pair with AIN2, or as a pseudodifferential input referenced to AINCOM.
12 AIN2 passive Analog input that acts as the negative input of a fully differential pair with AIN1, or as a pseudodifferential input referenced to AINCOM.
13 AIN3 passive Analog input that acts as the positive input of a fully differential pair with AIN4, or as a pseudodifferential input referenced to AINCOM.
14 AIN4 passive Analog input that acts as the negative input of a fully differential pair with AIN3, or as a pseudodifferential input referenced to AINCOM.
15 REFIN1(+) passive Positive external reference input, which can lie between AVDD and AGND + 1 V; the part functions with a reference from 1 V to AVDD.
16 REFIN1(-) passive Negative reference input, which can lie anywhere between AGND and AVDD − 1 V.
17 BPDSW passive Bridge power-down switch to AGND.
18 AGND power_in Analog ground reference point.
19 DGND power_in Digital ground reference point.
20 AVDD power_in Analog supply voltage, 3 V to 5.25 V, independent of DVDD.
21 DVDD power_in Digital supply voltage, 2.7 V to 5.25 V, independent of AVDD.
22 SYNC input Logic input for synchronizing digital filters and analog modulators across multiple devices; it has an internal pull-up to DVDD and resets RDY high when low.
23 DOUT/RDY output Serial data output and data-ready output that goes low to indicate conversion completion; with CS low, data is placed on the SCLK falling edge and is valid on the SCLK rising edge.
24 DIN input Serial data input to the ADC input shift register, with register selection set by the communications register bits.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-24
Category Data Converters
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Nonlinearity (Gain = 1, AVDD = 5 V) -10 2 10 ppm of FSR Gain = 1 (printed 'Gain = 12'), AVDD = 5 V 3
Integral Nonlinearity (Gain = 1, AVDD = 3 V) -15 2 15 ppm of FSR Gain = 1 (printed 'Gain = 12'), AVDD = 3 V 3
Integral Nonlinearity (Gain > 1, AVDD = 5 V) -30 5 30 ppm of FSR Gain > 1, AVDD = 5 V 3
Integral Nonlinearity (Gain > 1, AVDD = 3 V) -30 12 30 ppm of FSR Gain > 1, AVDD = 3 V 3
Power Supply Rejection 95 110 dB Gain > 1, VIN = 1 V/gain 3
Common-Mode Rejection @ DC 100 dB Gain = 1, VIN = 1 V 3
Common-Mode Rejection @ DC 110 dB Gain > 1, VIN = 1 V/gain 3
Common-Mode Rejection @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 3
Normal Mode Rejection @ 50 Hz, 60 Hz (Sinc4, internal clock) 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 3
Normal Mode Rejection (Sinc4, internal clock) 74 dB 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz 3
Normal Mode Rejection @ 50 Hz (Sinc4, internal clock) 96 dB 50 Hz output data rate, 50 ± 1 Hz 3
Normal Mode Rejection @ 60 Hz (Sinc4, internal clock) 97 dB 60 Hz output data rate, 60 ± 1 Hz 3
No Missing Codes 24 Bits FS > 1, sinc4 filter 3
Full-Scale Calibration Limit 1.05 × FS V 6
Zero-Scale Calibration Limit -1.05 × FS V 6
Input Span 0.8 × FS V 6
Input Span 2.1 × FS V 6
Power Supply Voltage AVDD − AGND AVDD 3 5.25 V AVDD − AGND 6
Power Supply Voltage DVDD − DGND DVDD 2.7 5.25 V DVDD − DGND 6
AIDD Current AIDD 0.53 0.6 mA Gain = 1, buffer off 6
AIDD Current AIDD 0.75 0.85 mA Gain = 1, buffer on 6
AIDD Current AIDD 2.5 3.2 mA Gain = 8, buffer off 6
AIDD Current AIDD 3 3.6 mA Gain = 8, buffer on 6
AIDD Current AIDD 3.5 4.5 mA Gain = 16 to 128, buffer off 6
AIDD Current AIDD 4 5 mA Gain = 16 to 128, buffer on 6
DIDD Current DIDD 0.35 0.4 mA DVDD = 3 V 6
DIDD Current DIDD 0.5 0.6 mA DVDD = 5 V 6
IDD (Power-Down Mode) IDD 3 μA Power-down mode 6
AVDD to AGND -0.3 6.5 V 9
DVDD to AGND -0.3 6.5 V 9
AGND to DGND -0.3 0.3 V 9
Analog Input Voltage to AGND -0.3 V Upper limit printed as AVDD + 0.3 V 9
Reference Input Voltage to AGND -0.3 V Upper limit printed as AVDD + 0.3 V 9
Digital Input Voltage to DGND -0.3 V Upper limit printed as DVDD + 0.3 V 9
Digital Output Voltage to DGND -0.3 V Upper limit printed as DVDD + 0.3 V 9
AIN/Digital Input Current 10 mA 9
Operating Temperature Range -40 105 °C 9
Storage Temperature Range -65 150 °C 9
Maximum Junction Temperature 150 °C 9
Lead Temperature, Soldering Reflow 260 °C 9
Thermal Resistance Junction-to-Ambient θJA 128 °C/W 24-lead TSSOP, worst case, device soldered in circuit board 9
Thermal Resistance Junction-to-Case θJC 42 °C/W 24-lead TSSOP 9

CAD (KiCad official)

  • Symbol: AD7192BRUZ
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ad7192bruz-etched.step / ad7192bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7192bruz.step / ad7192bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (40 pp, sha256 43b1e320e1ddd07a, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF