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AD7190WBRUZ
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Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD7190WBRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24
AD7190WBRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLK1 | passive | When the master clock is provided by a crystal, the crystal is connected between MCLK1 and MCLK2, and MCLK1 is left unconnected when MCLK2 is driven with a CMOS clock. |
| 2 | MCLK2 | bidirectional | This pin makes the internal 4.92 MHz clock available or accepts a CMOS-compatible external clock, with a crystal tied across MCLK1 and MCLK2. |
| 3 | SCLK | input | Serial clock input with a Schmitt-triggered input for data transfers to and from the ADC, which may run continuously or non-continuously. |
| 4 | CS | input | Active low chip select input that selects the ADC and can be hardwired low to operate the interface in 3-wire mode. |
| 5 | P3 | output | General-purpose digital output bit referenced between AVDD and AGND. |
| 6 | P2 | output | General-purpose digital output bit referenced between AVDD and AGND. |
| 7 | P1/REFIN2(+) | output | General-purpose digital output bit referenced between AVDD and AGND, which becomes the positive reference input REFIN2(+) when REFSEL = 1 and can lie between AVDD and AGND + 1 V. |
| 8 | P0/REFIN2(-) | output | General-purpose digital output bit referenced between AVDD and AGND, which becomes the negative reference input REFIN2(-) when REFSEL = 1 and can lie between AGND and AVDD - 1 V. |
| 9 | NC | unconnected | No connect pin that should be tied to AGND. |
| 10 | AINCOM | passive | Common analog input to which AIN1 to AIN4 are referenced when the channels are configured for pseudo differential operation. |
| 11 | AIN1 | passive | Analog input that serves as the positive input of a fully differential pair with AIN2 or as a pseudo differential input referenced to AINCOM. |
| 12 | AIN2 | passive | Analog input that serves as the negative input of a fully differential pair with AIN1 or as a pseudo differential input referenced to AINCOM. |
| 13 | AIN3 | passive | Analog input that serves as the positive input of a fully differential pair with AIN4 or as a pseudo differential input referenced to AINCOM. |
| 14 | AIN4 | passive | Analog input that serves as the negative input of a fully differential pair with AIN3 or as a pseudo differential input referenced to AINCOM. |
| 15 | REFIN1(+) | passive | Positive reference input that can lie between AVDD and AGND + 1 V, with a nominal reference of AVDD and a functional range of 1 V to AVDD. |
| 16 | REFIN1(-) | passive | Negative reference input that can lie between AGND and AVDD - 1 V. |
| 17 | BPDSW | passive | Bridge power-down switch connected to AGND. |
| 18 | AGND | power_in | Analog ground reference point for the device. |
| 19 | DGND | power_in | Digital ground reference point for the device. |
| 20 | AVDD | power_in | Analog supply voltage of 4.75 V to 5.25 V that is independent of DVDD. |
| 21 | DVDD | power_in | Digital supply voltage of 2.7 V to 5.25 V that is independent of AVDD. |
| 22 | SYNC | input | Logic input that synchronizes the digital filters and analog modulators of multiple AD7190 devices, resetting the filter nodes while held low, and has an internal pull-up to DVDD. |
| 23 | DOUT/RDY | output | Serial data output that also serves as the data ready output, going low to indicate a completed conversion and clocking data out on the SCLK falling edge while CS is low. |
| 24 | DIN | input | Serial data input to the ADC input shift register, with data transferred to the control registers as selected by the communications register. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD supply voltage (AVDD-AGND) | AVDD | 4.75 | 5.25 | V | 3 | ||
| DVDD supply voltage (DVDD-DGND) | DVDD | 2.7 | 5.25 | V | 6 | ||
| AIDD current | AIDD | 1 | mA | gain = 1, buffer off | 6 | ||
| AIDD current | AIDD | 1.3 | mA | gain = 1, buffer on | 6 | ||
| AIDD current (WB Grade) | AIDD | 5 | mA | gain = 8, buffer off | 6 | ||
| AIDD current (WB Grade) | AIDD | 5.3 | mA | gain = 8, buffer on | 6 | ||
| AIDD current (WB Grade) | AIDD | 6.8 | mA | gain = 16 to 128, buffer off | 6 | ||
| AIDD current (WB Grade) | AIDD | 7.4 | mA | gain = 16 to 128, buffer on | 6 | ||
| DIDD current | DIDD | 0.4 | mA | DVDD = 3 V | 6 | ||
| DIDD current | DIDD | 0.6 | mA | DVDD = 5 V | 6 | ||
| Power-down mode current (WB Grade) | IDD | 5 | μA | Power-down mode | 6 | ||
| Integral nonlinearity (WB Grade) | -7 | 7 | ppm of FSR | 3 | |||
| Integral nonlinearity (WB Grade) | -30 | 30 | ppm of FSR | gain > 1 | 3 | ||
| Gain error (WB Grade) | -0.0075 | 0.0075 | % | 3 | |||
| Power supply rejection (WB Grade) | 95 | dB | Gain > 1, VIN = 1 V/gain | 3 | |||
| Common-mode rejection at DC | 100 | dB | Gain = 1, VIN = 1 V | 3 | |||
| Common-mode rejection at DC | 110 | dB | Gain > 1, VIN = 1 V/gain | 3 | |||
| Common-mode rejection at 50 Hz, 60 Hz | 120 | dB | 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz | 3 | |||
| Normal mode rejection, sinc4, internal clock | 100 | dB | 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz | 3 | |||
| Normal mode rejection, sinc4, internal clock | 74 | dB | 50 Hz output data rate, REJ60 = 1, 50 ± 1 Hz, 60 ± 1 Hz | 3 | |||
| Normal mode rejection, sinc4, internal clock | 96 | dB | 50 Hz output data rate, 50 ± 1 Hz | 3 | |||
| Normal mode rejection, sinc4, internal clock | 97 | dB | 60 Hz output data rate, 60 ± 1 Hz | 3 | |||
| No missing codes | 24 | Bits | FS > 1, sinc4 filter | 3 | |||
| Internal clock frequency tolerance | -4 | 4 | % | internal 4.92 MHz clock | 33 | ||
| Bridge power-down switch on resistance | 10 | Ω | 35 | ||||
| Bridge power-down switch continuous current | 30 | mA | continuous current | 35 | |||
| AVDD to AGND | AVDD | -0.3 | 6.5 | V | TA = 25°C | 9 | |
| DVDD to AGND | DVDD | -0.3 | 6.5 | V | TA = 25°C | 9 | |
| AGND to DGND | -0.3 | 0.3 | V | TA = 25°C | 9 | ||
| AIN/digital input current | 10 | mA | TA = 25°C | 9 | |||
| Operating temperature range | TA | -40 | 105 | °C | 9 | ||
| Storage temperature range | -65 | 150 | °C | 9 | |||
| Maximum junction temperature | 150 | °C | 9 | ||||
| Lead temperature, soldering reflow | 260 | °C | 9 | ||||
| Thermal resistance junction-to-ambient (24-lead TSSOP) | θJA | 128 | °C/W | device soldered in circuit board, surface-mount package | 9 | ||
| Thermal resistance junction-to-case (24-lead TSSOP) | θJC | 42 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
AD7190WBRUZ - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad7190wbruz-etched.step/ad7190wbruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7190wbruz.step/ad7190wbruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (40 pp, sha256
178e899437f4cfdd, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).