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AD7190BRUZ

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Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7190BRUZ

Analog Devices · Analog To Digital Converters (ADC) · TSSOP-24

AD7190BRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MCLK1 input Master clock for the device, used with a crystal or an external clock at up to 4.92 MHz; MCLK1 is left unconnected when an external CMOS clock drives MCLK2.
2 MCLK2 output Master clock crystal connection; when a CMOS-compatible external clock is applied here, MCLK1 must be left unconnected.
3 SCLK input Serial clock input for the serial interface, a Schmitt-triggered input that clocks data to and from the device.
4 CS input Chip select input, active low; when CS is high, DOUT/RDY is placed in high impedance and the serial interface is disabled.
5 P3 bidirectional General-purpose digital input/output referenced between DVDD and DGND.
6 P2 bidirectional General-purpose digital input/output referenced between DVDD and DGND.
7 P1/REFIN2(+) bidirectional General-purpose digital input/output P1; when REFSEL = 1 this pin is the positive reference input REFIN2(+), which must be within AGND + 1 V and AVDD.
8 P0/REFIN2(-) bidirectional General-purpose digital input/output P0; when REFSEL = 1 this pin is the negative reference input REFIN2(-), which must be within AGND and AVDD - 1 V.
9 NC unconnected No connect; this pin is not internally connected and should be tied to AGND or left floating.
10 AINCOM passive Common-mode/ground reference point for the analog inputs AIN1 to AIN4 when they are configured as pseudo-differential inputs.
11 AIN1 input Analog input channel 1, configurable as a differential input paired with AIN2 or as a pseudo-differential input referenced to AINCOM.
12 AIN2 input Analog input channel 2, configurable as a differential input paired with AIN1 or as a pseudo-differential input referenced to AINCOM.
13 AIN3 input Analog input channel 3, configurable as a differential input paired with AIN4 or as a pseudo-differential input referenced to AINCOM.
14 AIN4 input Analog input channel 4, configurable as a differential input paired with AIN3 or as a pseudo-differential input referenced to AINCOM.
15 REFIN1(+) input Positive reference input; must be within AGND + 1 V and AVDD, and the differential reference (REFIN1(+) - REFIN1(-)) must be at least 1 V and no more than AVDD.
16 REFIN1(−) input Negative reference input; must be within AGND and AVDD - 1 V.
17 BPDSW passive Bridge power-down switch; connected to AGND when closed, referenced to AGND.
18 AGND power_in Analog ground reference for the analog circuitry; decouple AVDD to this pin.
19 DGND power_in Digital ground reference for the digital circuitry.
20 AVDD power_in Analog supply voltage, 4.75 V to 5.25 V; decouple to AGND.
21 DVDD power_in Digital supply voltage, 2.7 V to 5.25 V; decouple to DGND.
22 SYNC input Logic input that synchronizes the digital filter and analog modulator, referenced to DVDD and DGND, used to synchronize multiple devices.
23 DOUT/RDY tri_state Serial data output and data-ready output; drives the conversion data and goes low to indicate new data is ready, and is high impedance when CS is high.
24 DIN input Serial data input for writing to the on-chip registers through the serial interface.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-24
Category Data Acquisition
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output update rate 4.7 4800 Hz 3
Output update rate, chop enabled, Sinc4 1.17 1200 Hz Chop enabled, Sinc4 filter 3
Output update rate, chop enabled, Sinc3 1.56 1600 Hz Chop enabled, Sinc3 filter 3
No missing codes resolution 24 bits Sinc4 filter, FS > 1 3
Integral nonlinearity INL -5 1 5 ppm of FSR Gain = 1 3
Integral nonlinearity INL -15 5 15 ppm of FSR Gain > 1 3
Gain error -0.005 0.001 0.005 % Gain = 1, AVDD = 5 V 3
Power supply rejection ratio PSRR 100 110 dB Gain > 1, VIN = 1 V/gain 3
Common-mode rejection, DC CMRR 100 dB Gain = 1, VIN = 1 V 3
Common-mode rejection, DC CMRR 110 dB Gain > 1, VIN = 1 V/gain 3
Common-mode rejection, 50 Hz and 60 Hz CMRR 120 dB 10 Hz output rate, 50 ± 1 Hz, 60 ± 1 Hz, Sinc4 3
Absolute analog input voltage, buffer disabled AIN -50 mV Buffer disabled; min AGND − 50 mV, max AVDD + 50 mV 4
Absolute analog input voltage, buffer enabled AIN 250 mV Buffer enabled; min AGND + 250 mV, max AVDD − 250 mV 4
Analog input leakage current -2 2 nA Gain = 1 4
REFIN(x) reference input voltage REFIN 1 V Gain > 1; max AVDD 4
REFIN(x) common-mode range REFIN -50 mV Min AGND − 50 mV; max AVDD + 50 mV 4
Reference detect threshold 0.3 0.6 V REFDET function 5
Bridge switch on-resistance RON 10 Ω 5
Bridge switch continuous current 30 mA Continuous current 5
Digital output high voltage, P0-P3 VOH 4 V AVDD = 5 V, ISOURCE = 200 μA 5
Digital output low voltage, P0-P3 VOL 0.4 V AVDD = 5 V, ISINK = 800 μA 5
Digital output leakage current, P0-P3 -100 100 nA 5
Digital input low voltage VINL 0.8 V DVDD = 5 V 5
Digital input high voltage VINH 3.5 V DVDD = 5 V 5
MCLK internal clock frequency tolerance -4 4 % Nominal 4.92 MHz internal clock 5
External clock frequency, minimum 2.4576 MHz Nominal 4.9152 MHz external clock 5
External clock frequency, maximum 5.12 MHz Nominal 4.9152 MHz external clock 5
Analog supply current, buffer disabled AIDD 0.85 1 mA Gain = 1, buffer disabled 6
Analog supply current, buffer enabled AIDD 5.5 6.75 mA Gain 16 to 128, buffer enabled 6
Digital supply current DIDD 0.5 0.6 mA DVDD = 5 V 6
Power-down supply current IDD 2 μA Power-down, TMIN to TMAX 6
Analog supply voltage (AVDD − AGND) AVDD 4.75 5.25 V 6
Digital supply voltage (DVDD − DGND) DVDD 2.7 5.25 V 6
Operating temperature range TA -40 105 °C Industrial grade 1
AVDD to AGND AVDD -0.3 6.5 V 9
DVDD to AGND DVDD -0.3 6.5 V 9
AGND to DGND -0.3 0.3 V 9
Analog input voltage -0.3 V Relative to AGND; max AVDD + 0.3 V 9
REFIN voltage -0.3 V Relative to AGND; max AVDD + 0.3 V 9
Digital input voltage -0.3 V Relative to DGND; max DVDD + 0.3 V 9
Digital output voltage -0.3 V Relative to DGND; max DVDD + 0.3 V 9
Analog input / digital input current 10 mA 9
Storage temperature range -65 150 °C 9
Junction temperature 150 °C 9
Lead temperature, soldering 260 °C Reflow soldering 9
Thermal resistance, junction-to-ambient θJA 128 °C/W 24-lead TSSOP 9
Thermal resistance, junction-to-case θJC 42 °C/W 24-lead TSSOP 9
CS falling edge to DOUT/RDY valid t1 60 ns DVDD = 4.75 V to 5.25 V 7
CS falling edge to DOUT/RDY valid t1 80 ns DVDD = 2.7 V to 3.6 V 7
SCLK falling edge to data valid t2 60 ns DVDD = 4.75 V to 5.25 V 7
SCLK falling edge to data valid t2 80 ns DVDD = 2.7 V to 3.6 V 7
SCLK high pulse width t3 100 ns 7
SCLK low pulse width t4 100 ns 7
CS to SCLK timing t5 10 ns 7
SCLK timing t7 10 ns 7
CS to SCLK setup timing t8 0 ns 7
DIN setup to SCLK rising edge t9 30 ns 7
DIN hold after SCLK rising edge t10 25 ns 7
SCLK to CS hold timing t11 0 ns 7

CAD (KiCad official)

  • Symbol: AD7190BRUZ
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: ad7190bruz-etched.step / ad7190bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7190bruz.step / ad7190bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (40 pp, sha256 0e532c94b1a5fc5a, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF