AD7172-2BRUZ-RL7

{
  "slug": "ad7172-2bruz-rl7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ad7172-2bruz-rl7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ad7172-2bruz-rl7.kicad_sym",
    "ad7172-2bruz-rl7.kicad_mod",
    "ad7172-2bruz-rl7.glb",
    "ad7172-2bruz-rl7.step",
    "ad7172-2bruz-rl7.lbr",
    "docs/hero.png",
    "docs/ad7172-2bruz-rl7-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
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    "ad7172-2bruz-rl7-hero.overlay.json",
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  "component": {
    "mpn": "AD7172-2BRUZ-RL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-24",
    "pin_count": 24,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884884996046848",
    "parts": {
      "symbol": "ad7172-2bruz-rl7.kicad_sym",
      "footprint": "ad7172-2bruz-rl7.kicad_mod",
      "model_3d": "ad7172-2bruz-rl7-hero.glb",
      "model_3d_plain": "ad7172-2bruz-rl7-etched.glb",
      "model_3d_step": "ad7172-2bruz-rl7-etched.step",
      "model_3d_step_plain": "ad7172-2bruz-rl7.step",
      "lbr": "ad7172-2bruz-rl7.lbr"
    },
    "distributor_links": {
      "lcsc": "C495344",
      "digikey": "505-AD7172-2BRUZ-RL7TR-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T21:30:33Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD7172-2BRUZ-RL7TR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AIN4",
        "type": "input",
        "description": "Analog input 4, selectable as a signal or common input through the crosspoint multiplexer."
      },
      {
        "number": "2",
        "name": "REF−",
        "type": "input",
        "description": "Negative reference input; the range is AVSS to AVDD1 − 1 V."
      },
      {
        "number": "3",
        "name": "REF+",
        "type": "input",
        "description": "Positive reference input; an external reference is applied between REF+ and REF−, with REF+ in the range AVSS + 1 V to AVDD1 and a reference amplitude of 1 V to AVDD1."
      },
      {
        "number": "4",
        "name": "REFOUT",
        "type": "output",
        "description": "Buffered output of the internal reference, 2.5 V relative to AVSS."
      },
      {
        "number": "5",
        "name": "REGCAPA",
        "type": "output",
        "description": "Analog LDO regulator output, decoupled to AVSS with 1 µF and 0.1 µF capacitors; not for external loading."
      },
      {
        "number": "6",
        "name": "AVSS",
        "type": "power_in",
        "description": "Negative analog supply, range −2.75 V to 0 V, nominally set to 0 V."
      },
      {
        "number": "7",
        "name": "AVDD1",
        "type": "power_in",
        "description": "Analog supply 1, 3.3 V or 5 V ±10% relative to AVSS; supplies the crosspoint multiplexer and the analog and reference input buffers."
      },
      {
        "number": "8",
        "name": "AVDD2",
        "type": "power_in",
        "description": "Analog supply 2, range 2 V to 5.5 V relative to AVSS; feeds the internal 1.8 V analog LDO for the ADC core."
      },
      {
        "number": "9",
        "name": "XTAL1",
        "type": "input",
        "description": "Crystal oscillator input 1, used with XTAL2/CLKIO when an external crystal is selected."
      },
      {
        "number": "10",
        "name": "XTAL2/CLKIO",
        "type": "bidirectional",
        "description": "Crystal input 2 / clock input or output, selected by the CLOCKSEL bits; external clock input must be at IOVDD logic level and the internal oscillator output is driven at IOVDD logic level."
      },
      {
        "number": "11",
        "name": "DOUT/RDY",
        "type": "output",
        "description": "Serial data output and data-ready output; it is tri-stated when CS is high, and when CS is low it goes low to indicate conversion complete."
      },
      {
        "number": "12",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to the ADC input shift register, with data clocked in on the rising edge of SCLK."
      },
      {
        "number": "13",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with Schmitt-trigger input, suitable for opto-isolated applications."
      },
      {
        "number": "14",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select input used to select the ADC; it can be hard-wired low for 3-wire operation."
      },
      {
        "number": "15",
        "name": "SYNC/ERROR",
        "type": "bidirectional",
        "description": "Synchronization input, error input/output, or general-purpose output configured through GPIOCON; its logic level is referenced to IOVDD and DGND rather than AVDD1 and AVSS."
      },
      {
        "number": "16",
        "name": "IOVDD",
        "type": "power_in",
        "description": "Digital input/output supply, range 2 V to 5.5 V, independent of AVDD2; if AVSS is set to −2.5 V, IOVDD must not exceed 3.6 V."
      },
      {
        "number": "17",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "18",
        "name": "REGCAPD",
        "type": "output",
        "description": "Digital LDO regulator output, for decoupling only, with 1 µF and 0.1 µF capacitors to DGND."
      },
      {
        "number": "19",
        "name": "GPIO0",
        "type": "bidirectional",
        "description": "General-purpose input/output 0, referenced between AVDD1 and AVSS."
      },
      {
        "number": "20",
        "name": "GPIO1",
        "type": "bidirectional",
        "description": "General-purpose input/output 1, referenced between AVDD1 and AVSS."
      },
      {
        "number": "21",
        "name": "AIN0",
        "type": "input",
        "description": "Analog input 0, selectable through the crosspoint multiplexer."
      },
      {
        "number": "22",
        "name": "AIN1",
        "type": "input",
        "description": "Analog input 1, selectable through the crosspoint multiplexer."
      },
      {
        "number": "23",
        "name": "AIN2",
        "type": "input",
        "description": "Analog input 2, selectable through the crosspoint multiplexer."
      },
      {
        "number": "24",
        "name": "AIN3",
        "type": "input",
        "description": "Analog input 3, selectable through the crosspoint multiplexer."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and names are taken from the Table 5 pin function description (pages 9-10). The pin diag; DOUT/RDY is typed as output (a DO pin per Table 5) although the datasheet states it is tri-stated wh; Descriptions are translated from the Chinese-language datasheet text and condensed to one sentence e",
          "1/24 pins cited to the wrong page (name found elsewhere): ['9:XTAL1@p9']"
        ],
        "pages_sent": 44,
        "cost_usd": 0.2426,
        "at": "2026-10-18T21:27:34"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884884996046848",
        "pages": 59,
        "sha256": "56686172bb2ab706",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 24,
        "described": 24,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad7172-2bruz-rl7-etched.step",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": 0.0,
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        "sha256": "798925571404917feab99f8a306718ed432fd28da8014d4e305bc914300f0750",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}