# AD7172-2BRUZ-RL7

**Analog Devices** · Analog To Digital Converters (ADC) · TSSOP-24

AD7172-2BRUZ-RL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AIN4 | input | Analog input 4, selectable as a signal or common input through the crosspoint multiplexer. |
| 2 | REF− | input | Negative reference input; the range is AVSS to AVDD1 − 1 V. |
| 3 | REF+ | input | Positive reference input; an external reference is applied between REF+ and REF−, with REF+ in the range AVSS + 1 V to AVDD1 and a reference amplitude of 1 V to AVDD1. |
| 4 | REFOUT | output | Buffered output of the internal reference, 2.5 V relative to AVSS. |
| 5 | REGCAPA | output | Analog LDO regulator output, decoupled to AVSS with 1 µF and 0.1 µF capacitors; not for external loading. |
| 6 | AVSS | power_in | Negative analog supply, range −2.75 V to 0 V, nominally set to 0 V. |
| 7 | AVDD1 | power_in | Analog supply 1, 3.3 V or 5 V ±10% relative to AVSS; supplies the crosspoint multiplexer and the analog and reference input buffers. |
| 8 | AVDD2 | power_in | Analog supply 2, range 2 V to 5.5 V relative to AVSS; feeds the internal 1.8 V analog LDO for the ADC core. |
| 9 | XTAL1 | input | Crystal oscillator input 1, used with XTAL2/CLKIO when an external crystal is selected. |
| 10 | XTAL2/CLKIO | bidirectional | Crystal input 2 / clock input or output, selected by the CLOCKSEL bits; external clock input must be at IOVDD logic level and the internal oscillator output is driven at IOVDD logic level. |
| 11 | DOUT/RDY | output | Serial data output and data-ready output; it is tri-stated when CS is high, and when CS is low it goes low to indicate conversion complete. |
| 12 | DIN | input | Serial data input to the ADC input shift register, with data clocked in on the rising edge of SCLK. |
| 13 | SCLK | input | Serial clock input with Schmitt-trigger input, suitable for opto-isolated applications. |
| 14 | CS | input | Active-low chip select input used to select the ADC; it can be hard-wired low for 3-wire operation. |
| 15 | SYNC/ERROR | bidirectional | Synchronization input, error input/output, or general-purpose output configured through GPIOCON; its logic level is referenced to IOVDD and DGND rather than AVDD1 and AVSS. |
| 16 | IOVDD | power_in | Digital input/output supply, range 2 V to 5.5 V, independent of AVDD2; if AVSS is set to −2.5 V, IOVDD must not exceed 3.6 V. |
| 17 | DGND | power_in | Digital ground. |
| 18 | REGCAPD | output | Digital LDO regulator output, for decoupling only, with 1 µF and 0.1 µF capacitors to DGND. |
| 19 | GPIO0 | bidirectional | General-purpose input/output 0, referenced between AVDD1 and AVSS. |
| 20 | GPIO1 | bidirectional | General-purpose input/output 1, referenced between AVDD1 and AVSS. |
| 21 | AIN0 | input | Analog input 0, selectable through the crosspoint multiplexer. |
| 22 | AIN1 | input | Analog input 1, selectable through the crosspoint multiplexer. |
| 23 | AIN2 | input | Analog input 2, selectable through the crosspoint multiplexer. |
| 24 | AIN3 | input | Analog input 3, selectable through the crosspoint multiplexer. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | Data Acquisition |
| Pins | 24 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral nonlinearity (INL) | INL | -5 | 2 | 5 | FSR的ppm |  | 3 |
| Offset error |  | -40 |  | 40 | µV | Internal short | 3 |
| Offset drift |  | -65 |  | 65 | nV/°C | Internal short | 3 |
| Gain error |  | -45 | 5 | 45 | FSR的ppm | AVDD1 = 5 V | 3 |
| Gain drift |  | -0.5 | 0.2 | 0.5 | ppm/°C |  | 3 |
| Analog input current, input buffer disabled |  | -6 |  | 6 | µA/V | Input buffer disabled | 3 |
| Analog input current, input buffer enabled |  | -5 |  | 5 | nA | Input buffer enabled | 3 |
| Initial accuracy, REFOUT |  | -0.12 |  | 0.12 | V的百分比 | REFOUT, TA = 25°C | 3 |
| Reference temperature coefficient, 0°C to 105°C |  | -5 | 2 | 5 | ppm/°C | 0°C to 105°C | 3 |
| Reference temperature coefficient, -40°C to +105°C |  | -10 | 3 | 10 | ppm/°C | -40°C to +105°C | 3 |
| Reference load current | ILOAD | -10 |  | 10 | mA |  | 3 |
| Short-circuit current, reference | ISC |  |  | 25 | mA |  | 3 |
| Output voltage, internal reference (REFOUT) |  |  | 2.5 |  | V | REFOUT relative to AVSS | 3 |
| External reference differential input range | VREF | 1 | 2.5 |  | V | VREF = (REF+) − (REF−); maximum printed as AVDD1 | 4 |
| Temperature sensor accuracy |  | -2 |  | 2 | °C | After user calibration at 25°C | 4 |
| Excitation current (source/sink) |  | -10 |  | 10 | µA | Analog input buffer must be enabled | 4 |
| GPIO input mode leakage current |  | -10 |  | 10 | µA | GPIO0, GPIO1 relative to AVSS | 4 |
| Internal clock accuracy |  | -2.5 |  | 2.5 | % |  | 4 |
| Crystal oscillator frequency |  | 14 | 16 | 16.384 | MHz |  | 4 |
| External clock (CLKIO) duty cycle |  | 30 | 50 | 70 | % |  | 4 |
| Logic input leakage current |  | -10 |  | 10 | µA |  | 4 |
| AVDD1 current, 5 V, buffers disabled, external reference |  |  | 0.23 | 0.27 | mA | AVDD1 = 5 V typ, 5.5 V max | 5 |
| AVDD1 current, 5 V, buffers enabled, internal reference |  |  | 1.9 | 2.35 | mA | AVDD1 = 5 V typ, 5.5 V max; AIN± and REF± buffers enabled, internal reference | 5 |
| AVDD2 current, internal reference |  |  | 1.3 | 1.45 | mA | Internal reference | 5 |
| IOVDD current, internal clock |  |  | 0.61 | 0.82 | mA | Internal clock | 5 |
| Absolute maximum: AVDD1, AVDD2 to AVSS |  | -0.3 |  | 6.5 | V |  | 8 |
| Absolute maximum: AVDD1 to DGND |  | -0.3 |  | 6.5 | V |  | 8 |
| Absolute maximum: IOVDD to DGND |  | -0.3 |  | 6.5 | V |  | 8 |
| Absolute maximum: IOVDD to AVSS |  | -0.3 |  | 7.5 | V |  | 8 |
| Absolute maximum: AVSS to DGND |  | -3.25 |  | 0.3 | V |  | 8 |
| Absolute maximum: analog input voltage to AVSS |  | -0.3 |  |  | V | Maximum printed as AVDD1 + 0.3 V | 8 |
| Absolute maximum: reference input voltage to AVSS |  | -0.3 |  |  | V | Maximum printed as AVDD1 + 0.3 V | 8 |
| Absolute maximum: digital input voltage to DGND |  | -0.3 |  |  | V | Maximum printed as IOVDD + 0.3 V | 8 |
| Absolute maximum: analog/digital input current |  |  |  | 10 | mA |  | 8 |
| Absolute maximum: storage temperature range |  | -65 |  | 150 | °C |  | 8 |
| Absolute maximum: maximum junction temperature |  |  |  | 150 | °C |  | 8 |
| ESD rating, HBM |  |  |  | 4 | kV | HBM | 8 |
| Recommended supply: AVDD1 to AVSS |  | 3 |  | 5.5 | V |  | 5 |
| Recommended supply: AVDD2 to AVSS |  | 2 |  | 5.5 | V |  | 5 |
| Recommended supply: AVSS to DGND |  | -2.75 |  | 0 | V |  | 5 |
| Recommended supply: IOVDD to DGND |  | 2 |  | 5.5 | V |  | 5 |
| Operating temperature range | TA | -40 |  | 105 | °C |  | 1 |
| CS falling edge to DOUT/RDY valid | t1 | 0 |  |  | ns |  | 6 |
| CS falling edge to DOUT/RDY valid | t1 |  |  | 15 | ns | IOVDD = 4.75 V to 5.5 V | 6 |
| CS falling edge to DOUT/RDY valid | t1 |  |  | 40 | ns | IOVDD = 2 V to 3.6 V | 6 |
| SCLK active edge to data valid delay | t2 | 0 |  |  | ns |  | 6 |
| SCLK active edge to data valid delay | t2 |  |  | 12.5 | ns | IOVDD = 4.75 V to 5.5 V | 6 |
| SCLK active edge to data valid delay | t2 |  |  | 25 | ns | IOVDD = 2 V to 3.6 V | 6 |
| SCLK high pulse width | t3 | 25 |  |  | ns |  | 6 |
| SCLK low pulse width | t4 | 25 |  |  | ns |  | 6 |
| Bus release time after CS inactive edge | t5 | 2.5 |  | 20 | ns |  | 6 |
| SCLK inactive edge to DOUT/RDY high | t7 | 10 |  |  | ns |  | 6 |
| CS falling edge to SCLK active edge setup | t8 | 0 |  |  | ns |  | 6 |
| Data valid to SCLK edge setup | t9 | 8 |  |  | ns |  | 6 |
| Data valid to SCLK edge hold | t10 | 8 |  |  | ns |  | 6 |
| SCLK edge to CS active edge hold | t11 | 5 |  |  | ns |  | 6 |
| Thermal resistance, junction to ambient, 1-layer JEDEC board | θJA |  | 149 |  | °C/W | 1-layer JEDEC board, 24-lead TSSOP | 8 |
| Thermal resistance, junction to ambient, 2-layer JEDEC board | θJA |  | 81 |  | °C/W | 2-layer JEDEC board, 24-lead TSSOP | 8 |

## CAD (KiCad official)

- Symbol: `AD7172-2BRUZ-RL7`
- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`
- 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files: `ad7172-2bruz-rl7-etched.step` / `ad7172-2bruz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7172-2bruz-rl7.step` / `ad7172-2bruz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884884996046848) (59 pp, sha256 `56686172bb2ab706`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7172-2bruz-rl7-datasheet.pdf)