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AD7124-8BCPZ

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Analog Devices Analog To Digital Converters (ADC), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AD7124-8BCPZ

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-32(5x5)

AD7124-8BCPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REGCAPD power_out Digital LDO regulator output; decouple this pin to DGND with a 0.1 µF capacitor.
2 IOVDD power_in Serial interface supply, 1.65 V to 3.6 V, independent of AVDD (for example, the interface can run at 1.65 V while AVDD is 3.6 V).
3 DGND power_in Digital ground reference point.
4 AIN0/IOUT/VBIAS passive Analog input 0, configurable as the positive or negative differential/pseudo-differential input; can also carry an internal excitation current (IOUT0 or IOUT1) or the VBIAS mid-supply bias voltage.
5 AIN1/IOUT/VBIAS passive Analog input 1, configurable as the positive or negative differential/pseudo-differential input; can also carry an internal excitation current (IOUT0 or IOUT1) or the VBIAS mid-supply bias voltage.
6 AIN2/IOUT/VBIAS/P1 passive Analog input 2, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can be configured as general-purpose digital output P1 referenced between AVSS and AVDD.
7 AIN3/IOUT/VBIAS/P2 passive Analog input 3, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can be configured as general-purpose digital output P2 referenced between AVSS and AVDD.
8 AIN4/IOUT/VBIAS/P3 passive Analog input 4, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can be configured as general-purpose digital output P3 referenced between AVSS and AVDD.
9 AIN5/IOUT/VBIAS/P4 passive Analog input 5, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can be configured as general-purpose digital output P4 referenced between AVSS and AVDD.
10 AIN6/IOUT/VBIAS passive Analog input 6, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
11 AIN7/IOUT/VBIAS passive Analog input 7, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
12 REFIN1(+) input Positive reference input 1; may lie between AVDD and AVSS + 1 V, with a nominal REFIN1 of 2.5 V and operation from 1 V up to AVDD.
13 REFIN1(-) input Negative reference input 1; may be any voltage between AVSS and AVDD − 1 V.
14 AIN8/IOUT/VBIAS passive Analog input 8, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
15 AIN9/IOUT/VBIAS passive Analog input 9, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
16 AIN10/IOUT/VBIAS passive Analog input 10, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
17 AIN11/IOUT/VBIAS passive Analog input 11, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
18 AIN12/IOUT/VBIAS passive Analog input 12, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
19 AIN13/IOUT/VBIAS passive Analog input 13, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS.
20 AIN14/IOUT/VBIAS/REFIN2(+) passive Analog input 14, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can serve as the positive reference input REFIN2(+) (nominal 2.5 V, usable from 1 V to AVDD, and no more than AVSS + 1 V).
21 AIN15/IOUT/VBIAS/REFIN2(-) passive Analog input 15, configurable as differential/pseudo-differential input; can also carry IOUT0/IOUT1 or VBIAS, and can serve as the negative reference input REFIN2(−), which may be any voltage between AVSS and AVDD − 1 V.
22 REFOUT power_out Buffered output of the internal 2.5 V reference; requires a 0.1 µF decoupling capacitor when the internal reference is enabled.
23 AVSS power_in Analog supply voltage; AVDD is referenced to AVSS, which may be below 0 V for dual supplies (e.g., −1.8 V with AVDD at +1.8 V), with AVDD − AVSS between 2.7 V and 3.6 V in medium/low power mode and 2.9 V to 3.6 V in full power mode.
24 REGCAPA power_out Analog LDO regulator output; decouple to AVSS with a 0.1 µF capacitor.
25 PSW passive Low-side power switch connected to AVSS, used to switch off a bridge sensor between conversions (rated for 30 mA continuous, on-resistance up to 10 Ω).
26 AVDD power_in Analog supply voltage, referenced to AVSS.
27 SYNC input Synchronization logic input; holding it low resets the digital filter and modulator (for at least 4 master clock periods), and it can be used to synchronize multiple devices.
28 DOUT/RDY output Serial data output and data-ready output; the line goes low when a conversion is complete and can drive a processor interrupt, and it is clocked on SCLK falling edges with data valid on rising edges while CS is low.
29 DIN input Serial data input to the ADC input shift register; the communications register bits select the target register.
30 SCLK input Serial clock input with a Schmitt-trigger input (suitable for opto-isolated use) that may be continuous or non-continuous.
31 CLK bidirectional Clock input/output; provides the internal clock output or accepts an external clock when the internal clock is disabled, allowing multiple ADCs to be driven by the same clock for synchronized conversions.
32 CS input Active-low chip select input used to select the ADC on a shared serial bus; it may be hard-wired low for three-wire operation when SPI diagnostics are not used.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-32(5x5)
Category Data Acquisition
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-down mode current 5 µA 1
Supply voltage (single supply) 2.7 3.6 V 1
Operating temperature range -40 105 °C 1

CAD (KiCad official)

  • Symbol: AD7124-8BCPZ
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: ad7124-8bcpz-etched.step / ad7124-8bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7124-8bcpz.step / ad7124-8bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (91 pp, sha256 750fadb6dc6b4c99, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF