component
AD7124-4BRUZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "AD7124-4BRUZ-RL7",
"brief": "Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"mpn": "AD7124-4BRUZ-RL7",
"manufacturer": "Analog Devices",
"package": "TSSOP-24",
"pin_count": 24,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
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"pins": [
{
"number": "1",
"name": "DIN",
"type": "input",
"description": "Serial data input to the ADC input shift register; the communications register register-select bits determine which control register the data is transferred to."
},
{
"number": "2",
"name": "SCLK",
"type": "input",
"description": "Serial clock input for ADC data transfers, with a Schmitt-triggered input suitable for opto-isolated applications; it may be continuous or non-continuous."
},
{
"number": "3",
"name": "CLK",
"type": "bidirectional",
"description": "Clock input/output: the internal 614.4 kHz clock can be made available here, or the internal clock can be disabled and the ADC driven by an external clock."
},
{
"number": "4",
"name": "CS",
"type": "input",
"description": "Active-low chip select that selects the ADC; it can be hardwired low for 3-wire operation when SPI diagnostics are unused."
},
{
"number": "5",
"name": "REGCAPD",
"type": "power_out",
"description": "Digital LDO regulator output that must be decoupled to DGND with a 0.1 µF capacitor."
},
{
"number": "6",
"name": "IOVDD",
"type": "power_in",
"description": "Serial interface supply voltage of 1.65 V to 3.6 V, independent of AVDD."
},
{
"number": "7",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference point."
},
{
"number": "8",
"name": "AIN0/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 0 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails."
},
{
"number": "9",
"name": "AIN1/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 1 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails."
},
{
"number": "10",
"name": "AIN2/IOUT/VBIAS/P1",
"type": "passive",
"description": "Analog input 2, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P1 referenced between AVSS and AVDD."
},
{
"number": "11",
"name": "AIN3/IOUT/VBIAS/P2",
"type": "passive",
"description": "Analog input 3, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P2 referenced between AVSS and AVDD."
},
{
"number": "12",
"name": "REFIN1(+)",
"type": "passive",
"description": "Positive external reference input; the nominal REFIN1(+) − REFIN1(−) is 2.5 V, the device functions with a reference from 0.5 V to AVDD, and REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V."
},
{
"number": "13",
"name": "REFIN1(−)",
"type": "passive",
"description": "Negative external reference input, which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "14",
"name": "AIN4/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 4, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails."
},
{
"number": "15",
"name": "AIN5/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 5, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails."
},
{
"number": "16",
"name": "AIN6/IOUT/VBIAS/REFIN2(+)",
"type": "passive",
"description": "Analog input 6, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the positive reference input for REFIN2(±), with the nominal 2.5 V reference functioning from 0.5 V to AVDD."
},
{
"number": "17",
"name": "AIN7/IOUT/VBIAS/REFIN2(−)",
"type": "passive",
"description": "Analog input 7, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the negative reference input for REFIN2(±), which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "18",
"name": "REFOUT",
"type": "output",
"description": "Buffered output of the internal 2.5 V voltage reference."
},
{
"number": "19",
"name": "AVSS",
"type": "power_in",
"description": "Analog supply ground; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS may be taken below 0 V (e.g., −1.8 V) for a dual supply."
},
{
"number": "20",
"name": "REGCAPA",
"type": "power_out",
"description": "Analog LDO regulator output that must be decoupled to AVSS with a 0.1 µF capacitor."
},
{
"number": "21",
"name": "PSW",
"type": "passive",
"description": "Low-side power switch to AVSS, rated for 30 mA continuous current with 10 Ω maximum on-resistance."
},
{
"number": "22",
"name": "AVDD",
"type": "power_in",
"description": "Analog supply voltage relative to AVSS, 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode."
},
{
"number": "23",
"name": "SYNC",
"type": "input",
"description": "Synchronization logic input; when low it resets the digital filter, filter control and calibration control logic and holds the modulator in reset, and it also resets RDY high."
},
{
"number": "24",
"name": "DOUT/RDY",
"type": "output",
"description": "Serial data output and data-ready output; the pin goes low to indicate conversion completion and, with CS low, data is placed on the SCLK falling edge and is valid on the SCLK rising edge."
}
],
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],
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"name": "AVDD to AVSS supply, Low Power Mode",
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"name": "Storage temperature range",
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{
"name": "Maximum junction temperature",
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"name": "Absolute input current, buffered, Low Power Mode",
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{
"name": "Differential input current, buffered, Low Power Mode",
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"name": "Absolute input current, buffered, Mid Power Mode",
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"name": "Differential input current, buffered, Full Power Mode",
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"name": "Absolute input current, unbuffered",
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"name": "Reference input current, buffered, Full Power Mode",
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"name": "Excitation current initial tolerance",
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"name": "Excitation current matching",
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"name": "Excitation current drift matching",
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"name": "Low-side power switch on resistance",
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{
"name": "Internal clock frequency tolerance (614.4 kHz nominal)",
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