component
AD7124-4BRUZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ad7124-4bruz-rl7",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Analog To Digital Converters (ADC), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"data acquisition",
"ad7124-4bruz-rl7",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ad7124-4bruz-rl7.kicad_sym",
"ad7124-4bruz-rl7.kicad_mod",
"ad7124-4bruz-rl7.glb",
"ad7124-4bruz-rl7.step",
"ad7124-4bruz-rl7.lbr",
"docs/hero.png",
"docs/ad7124-4bruz-rl7-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ad7124-4bruz-rl7-hero.glb",
"ad7124-4bruz-rl7-hero.overlay.json",
"ad7124-4bruz-rl7-etched.glb"
],
"component": {
"mpn": "AD7124-4BRUZ-RL7",
"manufacturer": "Analog Devices",
"package": "TSSOP-24",
"pin_count": 24,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885740729720832",
"parts": {
"symbol": "ad7124-4bruz-rl7.kicad_sym",
"footprint": "ad7124-4bruz-rl7.kicad_mod",
"model_3d": "ad7124-4bruz-rl7-hero.glb",
"model_3d_plain": "ad7124-4bruz-rl7-etched.glb",
"model_3d_step": "ad7124-4bruz-rl7-etched.step",
"model_3d_step_plain": "ad7124-4bruz-rl7.step",
"lbr": "ad7124-4bruz-rl7.lbr"
},
"distributor_links": {
"lcsc": "C462194",
"digikey": "505-AD7124-4BRUZ-RL7TR-ND",
"mouser": "584-AD7124-4BRUZ-RL7"
},
"distributor_check": {
"checked_at": "2026-10-18T04:05:28Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD7124-4BRUZ-RL7TR-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "584-AD7124-4BRUZ-RL7",
"status": "found",
"lifecycle": "Restricted Availability"
}
},
"pins": [
{
"number": "1",
"name": "DIN",
"type": "input",
"description": "Serial data input to the ADC input shift register; the communications register register-select bits determine which control register the data is transferred to."
},
{
"number": "2",
"name": "SCLK",
"type": "input",
"description": "Serial clock input for ADC data transfers, with a Schmitt-triggered input suitable for opto-isolated applications; it may be continuous or non-continuous."
},
{
"number": "3",
"name": "CLK",
"type": "bidirectional",
"description": "Clock input/output: the internal 614.4 kHz clock can be made available here, or the internal clock can be disabled and the ADC driven by an external clock."
},
{
"number": "4",
"name": "CS",
"type": "input",
"description": "Active-low chip select that selects the ADC; it can be hardwired low for 3-wire operation when SPI diagnostics are unused."
},
{
"number": "5",
"name": "REGCAPD",
"type": "power_out",
"description": "Digital LDO regulator output that must be decoupled to DGND with a 0.1 µF capacitor."
},
{
"number": "6",
"name": "IOVDD",
"type": "power_in",
"description": "Serial interface supply voltage of 1.65 V to 3.6 V, independent of AVDD."
},
{
"number": "7",
"name": "DGND",
"type": "power_in",
"description": "Digital ground reference point."
},
{
"number": "8",
"name": "AIN0/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 0 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails."
},
{
"number": "9",
"name": "AIN1/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 1 (positive or negative terminal of a differential or pseudo-differential input), alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, midway between the analog supply rails."
},
{
"number": "10",
"name": "AIN2/IOUT/VBIAS/P1",
"type": "passive",
"description": "Analog input 2, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P1 referenced between AVSS and AVDD."
},
{
"number": "11",
"name": "AIN3/IOUT/VBIAS/P2",
"type": "passive",
"description": "Analog input 3, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage, or configured as general-purpose output P2 referenced between AVSS and AVDD."
},
{
"number": "12",
"name": "REFIN1(+)",
"type": "passive",
"description": "Positive external reference input; the nominal REFIN1(+) − REFIN1(−) is 2.5 V, the device functions with a reference from 0.5 V to AVDD, and REFIN1(+) can be anywhere between AVDD and AVSS + 0.5 V."
},
{
"number": "13",
"name": "REFIN1(−)",
"type": "passive",
"description": "Negative external reference input, which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "14",
"name": "AIN4/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 4, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails."
},
{
"number": "15",
"name": "AIN5/IOUT/VBIAS",
"type": "passive",
"description": "Analog input 5, alternatively the IOUT0/IOUT1 excitation current output or the VBIAS bias voltage midway between the analog supply rails."
},
{
"number": "16",
"name": "AIN6/IOUT/VBIAS/REFIN2(+)",
"type": "passive",
"description": "Analog input 6, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the positive reference input for REFIN2(±), with the nominal 2.5 V reference functioning from 0.5 V to AVDD."
},
{
"number": "17",
"name": "AIN7/IOUT/VBIAS/REFIN2(−)",
"type": "passive",
"description": "Analog input 7, alternatively the IOUT0/IOUT1 excitation current output or VBIAS, and also the negative reference input for REFIN2(±), which can be anywhere between AVSS and AVDD − 0.5 V."
},
{
"number": "18",
"name": "REFOUT",
"type": "output",
"description": "Buffered output of the internal 2.5 V voltage reference."
},
{
"number": "19",
"name": "AVSS",
"type": "power_in",
"description": "Analog supply ground; AVDD − AVSS must be 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode, and AVSS may be taken below 0 V (e.g., −1.8 V) for a dual supply."
},
{
"number": "20",
"name": "REGCAPA",
"type": "power_out",
"description": "Analog LDO regulator output that must be decoupled to AVSS with a 0.1 µF capacitor."
},
{
"number": "21",
"name": "PSW",
"type": "passive",
"description": "Low-side power switch to AVSS, rated for 30 mA continuous current with 10 Ω maximum on-resistance."
},
{
"number": "22",
"name": "AVDD",
"type": "power_in",
"description": "Analog supply voltage relative to AVSS, 2.7 V to 3.6 V in mid or low power mode and 2.9 V to 3.6 V in full power mode."
},
{
"number": "23",
"name": "SYNC",
"type": "input",
"description": "Synchronization logic input; when low it resets the digital filter, filter control and calibration control logic and holds the modulator in reset, and it also resets RDY high."
},
{
"number": "24",
"name": "DOUT/RDY",
"type": "output",
"description": "Serial data output and data-ready output; the pin goes low to indicate conversion completion and, with CS low, data is placed on the SCLK falling edge and is valid on the SCLK rising edge."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Regulator outputs (REGCAPD, REGCAPA) are typed power_out as a judgment call; the datasheet only says; Analog inputs, reference inputs and the PSW switch have no native KiCad ERC class; they are typed pa; CLK is typed bidirectional because the datasheet describes it as both clock input and clock output."
],
"pages_sent": 20,
"cost_usd": 0.1473,
"at": "2026-10-18T04:03:25"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885740729720832",
"pages": 93,
"sha256": "9f9df9294d9f4ad3",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 24,
"described": 24,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad7124-4bruz-rl7.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
7.8,
0.97
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",
"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad7124-4bruz-rl7-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6.4,
7.8,
0.97
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "ecb3ba0819fe1ecd40566aa871b4b24d5f0ea18ff077b1f8f0d6c7d1af6ff703",
"checked": "2026-10-18",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}