AD5930YRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	FSADJUST	passive	Full-scale adjust control; an external RSET (6.8 kΩ typical) is connected between this pin and AGND to set full-scale DAC current IOUTFULL-SCALE = 18 × VREFOUT/RSET with VREFOUT = 1.20 V nominal.
2	REF	bidirectional	Voltage reference input or output; internal 1.18 V reference is available here or can be overdriven by an external reference, with a 10 nF decoupling capacitor to AGND.
3	COMP	passive	DAC bias pin used for decoupling the DAC bias voltage to AVDD.
4	AVDD	power_in	Positive power supply for the analog section, 2.3 V to 5.5 V, with a 0.1 µF decoupling capacitor to AGND.
5	DVDD	power_in	Positive power supply for the digital section, 2.3 V to 5.5 V, with a 0.1 µF decoupling capacitor to DGND.
6	CAP/2.5V	passive	Output of the on-board 2.5 V regulator for digital circuitry generated from DVDD, requiring a typically 100 nF capacitor to DGND; can be shorted to DVDD if DVDD is 2.7 V or less.
7	DGND	power_in	Ground for all digital circuitry, excluding digital output buffers.
8	MCLK	input	Digital clock input; DDS output frequencies are a binary fraction of MCLK, which determines output frequency accuracy and phase noise.
9	SYNCOUT	output	Digital output for sweep status (end of sweep or frequency increments), selectable via the control register and enabled by setting SYNCOPEN to 1.
10	MSBOUT	output	Digital output giving the inverted MSB of the DAC data, enabled by setting MSBOUTEN in the control register to 1.
11	DGND O/P	power_in	Separate DGND connection for the digital output buffers; connect to DGND.
12	INTERRUPT	input	Digital input acting as an interrupt during a sweep; a low-to-high transition sampled by the internal MCLK resets the state machines and sends the DAC output to midscale.
13	CTRL	input	Digital input with triple function for initialization, start and external frequency increments; a low-to-high transition sampled by MCLK starts the preprogrammed sweep.
14	SDATA	input	Serial data input; the 16-bit word is applied with the register address first followed by data MSB to LSB.
15	SCLK	input	Serial clock input; data is clocked in on each falling SCLK edge.
16	FSYNC	input	Active-low frame synchronization control input; taking it low signals that a new word is being loaded.
17	STANDBY	input	Active-high standby input that disables the internal MCLK and powers down the reference DAC and regulator, giving typically 20 µA shutdown current after a reset.
18	AGND	power_in	Ground for all analog circuitry.
19	IOUT	output	High-impedance current source output; connect a nominal 200 Ω load to AGND with a recommended 20 pF capacitor to AGND, and a differential signal is available with IOUTB.
20	IOUTB	output	Complementary current output to IOUT, preferably tied through a 200 Ω resistor to AGND (or directly to AGND), with a recommended 20 pF capacitor to AGND.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20
Category	ADC/DAC/Data Conversion
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage AVDD/DVDD	AVDD/DVDD	2.3		5.5	V	fMCLK = 50 MHz, fOUT = fMCLK/7	5
Analog supply current	IAA		3.8	4	mA	fMCLK = 50 MHz, fOUT = fMCLK/7	5
Digital supply current	IDD		2.4	2.7	mA	fMCLK = 50 MHz, fOUT = fMCLK/7	5
Total supply current	IAA + IDD		6.2	6.7	mA	fMCLK = 50 MHz, fOUT = fMCLK/7	5
Low power sleep mode current, MCLK = 0 V			20	85	µA	All outputs powered down, MCLK = 0 V, serial interface active; device is reset before putting into standby	5
Low power sleep mode current, MCLK active			140	240	µA	All outputs powered down, MCLK active, serial interface active; device is reset before putting into standby	5
MCLK period	t1	20			ns	MCLK period	6
MCLK high duration	t2	8			ns	MCLK high duration	6
MCLK low duration	t3	8			ns	MCLK low duration	6
SCLK period	t4	25			ns	SCLK period	6
SCLK high time	t5	10			ns	SCLK high time	6
SCLK low time	t6	10			ns	SCLK low time	6
FSYNC to SCLK falling edge setup time	t7	5			ns	FSYNC to SCLK falling edge setup time	6
FSYNC to SCLK hold time	t8	10			ns	FSYNC to SCLK hold time	6
Data setup time	t9	5			ns	Data setup time	6
Data hold time	t10	3			ns	Data hold time	6
Minimum CTRL pulse width	t11	2			ns	Minimum CTRL pulse width; printed as 2 x t1	6
CTRL rising edge to MCLK falling edge setup time	t12	0			ns	CTRL rising edge to MCLK falling edge setup time	6
MCLK falling edge after 16th clock edge to MSB out	t17			20	ns	MCLK falling edge after 16th clock edge to MSB out	6
AVDD to AGND	AVDD	-0.3		6	V	TA = 25°C	8
DVDD to DGND	DVDD	-0.3		6	V	TA = 25°C	8
AGND to DGND		-0.3		0.3	V	TA = 25°C	8
CAP/2.5V to DGND		-0.3		2.75	V	TA = 25°C	8
Digital I/O voltage to DGND		-0.3			V	Upper limit DVDD + 0.3 V; TA = 25°C	8
Analog I/O voltage to AGND		-0.3			V	Upper limit AVDD + 0.3 V; TA = 25°C	8
Operating temperature range (Y version)		-40		125	°C	Automotive (Y Version)	8
Storage temperature range		-65		150	°C		8
Maximum junction temperature				150	°C		8
Reflow soldering (Pb-free)				300	°C	Reflow soldering (Pb-Free)	8
Thermal impedance junction to ambient	θJA		112		°C/W	TSSOP package, 4-layer board	8
Thermal impedance junction to case	θJC		27.6		°C/W	TSSOP package, 4-layer board	8
CTRL rising edge to IOUT/IOUTB delay (10 x t1)	t13		10		ns	Initial pulse, includes initialization; printed as 10 x t1	6
CTRL rising edge to IOUT/IOUTB delay (8 x t1)	t13		8		ns	Initial pulse, includes initialization; printed as 8 x t1	6

CAD (KiCad official)

Symbol: AD5930YRUZ
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ad5930yruz-etched.step / ad5930yruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5930yruz.step / ad5930yruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 bfd40c006f3fff15, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5930YRUZ

Verified AD5930YRUZ

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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