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AD5791BRUZ

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Analog Devices Digital To Analog Converters (DAC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD5791BRUZ

Analog Devices · Digital To Analog Converters (DAC) · TSSOP-20

AD5791BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INV passive Connection to the inverting input of an external amplifier; see the AD5791 Features section for further details.
2 VOUT output Analog output voltage of the DAC.
3 VREFPS input Positive reference sense voltage input; a voltage range of 5 V to VDD − 2.5 V can be connected, and a unity-gain amplifier must be connected at this pin in conjunction with VREFPF.
4 VREFPF input Positive reference force voltage input; a voltage range of 5 V to VDD − 2.5 V can be connected, and a unity-gain amplifier must be connected at this pin in conjunction with VREFPS.
5 VDD power_in Positive analog supply connection; a voltage range of 7.5 V to 16.5 V can be connected, and VDD should be decoupled to AGND.
6 RESET input Active-low reset logic input; asserting this pin returns the AD5791 to its power-on status.
7 CLR input Active-low clear logic input; asserting this pin sets the DAC register to a user-defined value (see Table 13) and updates the DAC output.
8 LDAC input Active-low load DAC logic input; when tied permanently low the output updates on the rising edge of SYNC, and LDAC must not be left unconnected.
9 VCC power_in Digital supply connection; a voltage range of 2.7 V to 5.5 V can be connected, and VCC should be decoupled to DGND.
10 IOVCC power_in Digital interface supply pin that sets the digital threshold levels; a voltage in the range of 1.71 V to 5.5 V can be connected, and IOVCC must not exceed VCC.
11 SDO output Serial data output; data is clocked out on the rising edge of the serial clock input.
12 SDIN input Serial data input to the 24-bit shift register; data is clocked in on the falling edge of the serial clock.
13 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge, with clock rates of up to 35 MHz.
14 SYNC input Active-low digital interface synchronization input; when SYNC is low it enables the input shift register, which is updated on the rising edge of SYNC.
15 DGND power_in Ground reference pin for digital circuitry.
16 VREFNF input Negative reference force voltage input; a voltage range of VSS + 2.5 V to 0 V can be connected, and a unity-gain amplifier must be connected at this pin in conjunction with VREFNS.
17 VREFNS input Negative reference sense voltage input; a voltage range of VSS + 2.5 V to 0 V can be connected, and a unity-gain amplifier must be connected at this pin in conjunction with VREFNF.
18 VSS power_in Negative analog supply connection; a voltage range of −16.5 V to −2.5 V can be connected, and VSS should be decoupled to AGND.
19 AGND power_in Ground reference pin for analog circuitry.
20 RFB passive Feedback connection for an external amplifier; see the AD5791 Features section for further details.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-20
Category Data Acquisition
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Nonlinearity Error (Relative Accuracy) -1 0.25 1 LSB B version, VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C 3
Integral Nonlinearity Error (Relative Accuracy) -1.5 0.25 1.5 LSB B version, VREFP = +10 V, VREFN = −10 V 3
Integral Nonlinearity Error (Relative Accuracy) -1.5 0.5 1.5 LSB B version, VREFP = 10 V, VREFN = 0 V 3
Integral Nonlinearity Error (Relative Accuracy) -3 1 3 LSB B version, VREFP = 5 V, VREFN = 0 V 3
Differential Nonlinearity Error -1 0.5 1 LSB VREFP = +10 V, VREFN = −10 V 3
Differential Nonlinearity Error -1.5 0.75 1.5 LSB VREFP = 10 V, VREFN = 0 V 3
Differential Nonlinearity Error -2.5 1 2.5 LSB VREFP = 5 V, VREFN = 0 V 3
Full-Scale Error -7 0.1 7 LSB VREFP = +10 V, VREFN = −10 V 3
Full-Scale Error -11 0.25 11 LSB VREFP = 10 V, VREFN = 0 V 3
Full-Scale Error -21 0.8 21 LSB VREFP = 5 V, VREFN = 0 V 3
Full-Scale Error -4 0.1 4 LSB VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C 3
Full-Scale Error -4 0.25 4 LSB VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C 3
Full-Scale Error -6 0.8 6 LSB VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C 3
Zero-Scale Error -7 0.1 7 LSB VREFP = +10 V, VREFN = −10 V 3
Zero-Scale Error -10 0.15 10 LSB VREFP = 10 V, VREFN = 0 V 3
Zero-Scale Error -21 0.75 21 LSB VREFP = 5 V, VREFN = 0 V 3
Zero-Scale Error -4 0.1 4 LSB VREFP = +10 V, VREFN = −10 V, TA = 0°C to 105°C 3
Zero-Scale Error -4 0.15 4 LSB VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C 3
Zero-Scale Error -6 0.75 6 LSB VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C 3
Gain Error -6 0.3 6 ppm FSR VREFP = +10 V, VREFN = −10 V 3
Gain Error -10 0.4 10 ppm FSR VREFP = 10 V, VREFN = 0 V 3
Gain Error -20 0.4 20 ppm FSR VREFP = 5 V, VREFN = 0 V 3
Gain Error -6 0.4 6 ppm FSR VREFP = 10 V, VREFN = 0 V, TA = 0°C to 105°C 3
Gain Error -7 0.4 7 ppm FSR VREFP = 5 V, VREFN = 0 V, TA = 0°C to 105°C 3
VREFP Input Range (max VDD − 2.5 V) VREFP 5 V 4
VREFN Input Range (min VSS + 2.5 V) VREFN 0 V 4
Input Current (individual logic pin) -1 1 µA 4
Output Low Voltage VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA 4
High Impedance Leakage Current (SDO) -1 1 µA 4
Positive Analog Supply Range VDD (max VSS + 33 V) VDD 7.5 V All digital inputs at DGND or IOVCC 4
Negative Analog Supply Range VSS (min VDD − 33 V) VSS -2.5 V All digital inputs at DGND or IOVCC 4
Digital Supply Range VCC VCC 2.7 5.5 V All digital inputs at DGND or IOVCC 4
Digital Interface Supply Range IOVCC IOVCC 1.71 5.5 V All digital inputs at DGND or IOVCC; IOVCC ≤ VCC 4
Positive Supply Current IDD IDD 4.2 5.2 mA All digital inputs at DGND or IOVCC 4
Negative Supply Current ISS ISS 4 4.9 mA All digital inputs at DGND or IOVCC 4
Digital Supply Current ICC ICC 600 900 µA All digital inputs at DGND or IOVCC 4
IOVCC Supply Current (SDO disabled) IOICC 52 140 µA All digital inputs at DGND or IOVCC; SDO disabled 4
DC Power Supply Rejection Ratio (VDD) -0.6 0.6 µV/V VDD ± 10%, VSS = 15 V 4
DC Power Supply Rejection Ratio (VSS) -0.6 0.6 µV/V VSS ± 10%, VDD = 15 V 4
Operating Temperature Range, Industrial TA -40 125 °C TA = 25°C, unless otherwise noted 7
Storage Temperature Range -65 150 °C TA = 25°C, unless otherwise noted 7
Maximum Junction Temperature TJ max TJ 150 °C TA = 25°C, unless otherwise noted 7
VDD to AGND -0.3 34 V TA = 25°C, unless otherwise noted 7
VSS to AGND -34 0.3 V TA = 25°C, unless otherwise noted 7
VDD to VSS -0.3 34 V TA = 25°C, unless otherwise noted 7
VCC to DGND -0.3 7 V TA = 25°C, unless otherwise noted 7
IOVCC to DGND (max VCC + 0.3 V or +7 V, whichever is less) -0.3 V TA = 25°C, unless otherwise noted 7
Digital Inputs to DGND (max IOVCC + 0.3 V or +7 V, whichever is less) -0.3 V TA = 25°C, unless otherwise noted 7
VOUT to AGND (max VDD + 0.3 V) -0.3 V TA = 25°C, unless otherwise noted 7
VREFPF to AGND (max VDD + 0.3 V) -0.3 V TA = 25°C, unless otherwise noted 7
VREFPS to AGND (max VDD + 0.3 V) -0.3 V TA = 25°C, unless otherwise noted 7
VREFNF to AGND (min VSS − 0.3 V) 0.3 V TA = 25°C, unless otherwise noted 7
VREFNS to AGND (min VSS − 0.3 V) 0.3 V TA = 25°C, unless otherwise noted 7
DGND to AGND -0.3 0.3 V TA = 25°C, unless otherwise noted 7
Thermal Impedance, junction-to-ambient θJA θJA 143 °C/W TSSOP package 7
Thermal Impedance, junction-to-case θJC θJC 45 °C/W TSSOP package 7

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing Abs ESD (Human Body Model) 1.5 kV Stresses at or above those listed under Absolute Maximum 7

CAD (KiCad official)

  • Symbol: AD5791BRUZ
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: ad5791bruz-etched.step / ad5791bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5791bruz.step / ad5791bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (27 pp, sha256 0d17ccf41a167767, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF