component
AD5780ACPZ
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-24(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Contents
README
markdownAD5780ACPZ
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-24(4x5)
AD5780ACPZ from Analog Devices, in a LFCSP-24(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | output | Analog output voltage of the DAC. |
| 2 | VREFP | input | Positive reference voltage input; a voltage in the range of 5 V to VDD − 2.5 V can be connected to this pin. |
| 3 | VDD | power_in | Positive analog supply connection; a voltage in the range of 7.5 V to 16.5 V can be connected and VDD must be decoupled to AGND. |
| 4 | RESET | input | Active low reset; asserting this pin returns the AD5780 to its power-on status. |
| 5 | VDD | power_in | Positive analog supply connection; a voltage in the range of 7.5 V to 16.5 V can be connected and VDD must be decoupled to AGND. |
| 6 | CLR | input | Active low input that sets the DAC register to a user defined value and updates the DAC output when asserted. |
| 7 | LDAC | input | Active low load DAC logic input that updates the DAC register and analog output; it must not be left unconnected. |
| 8 | VCC | power_in | Digital supply with a voltage range of 2.7 V to 5.5 V; VCC should be decoupled to DGND. |
| 9 | IOVCC | power_in | Digital interface supply to which the digital threshold levels are referenced; voltage range is 1.71 V to 5.5 V. |
| 10 | DNC | unconnected | Do not connect to this pin. |
| 11 | SDO | output | Serial data output; data is clocked out on the rising edge of the serial clock input. |
| 12 | SDIN | input | Serial data input to the 24-bit input shift register; data is clocked in on the falling edge of the serial clock. |
| 13 | SCLK | input | Serial clock input; data can be transferred at rates of up to 35 MHz. |
| 14 | SYNC | input | Level triggered active low frame synchronization input; the DAC is updated on the rising edge of SYNC. |
| 15 | DGND | power_in | Ground reference pin for digital circuitry. |
| 16 | VREFN | input | Negative reference voltage input. |
| 17 | VSS | power_in | Negative analog supply connection; a voltage in the range of −16.5 V to −2.5 V can be connected and VSS must be decoupled to AGND. |
| 18 | VSS | power_in | Negative analog supply connection; a voltage in the range of −16.5 V to −2.5 V can be connected and VSS must be decoupled to AGND. |
| 19 | AGND | power_in | Ground reference pin for analog circuitry. |
| 20 | RFB | passive | Feedback connection for an external amplifier. |
| 21 | DNC | unconnected | Do not connect to this pin. |
| 22 | DNC | unconnected | Do not connect to this pin. |
| 23 | DNC | unconnected | Do not connect to this pin. |
| 24 | INV | input | Inverting input connection for an external amplifier. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-24(4x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinearity Error (Relative Accuracy) | -2 | 2 | LSB | A grade, VREFx = ±10 V, +10 V, and +5 V | 3 | ||
| Differential Nonlinearity Error | -1 | 1 | LSB | A grade, VREFx = ±10 V, +10 V, and +5 V | 3 | ||
| Full-Scale Error | -3 | 3 | LSB | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Full-Scale Error | -5.5 | 0.5 | LSB | VREFP = 10 V, VREFN = 0 V | 3 | ||
| Full-Scale Error | -10 | 10 | LSB | VREFP = 5 V, VREFN = 0 V | 3 | ||
| Full-Scale Error Temperature Coefficient | -0.026 | 0.026 | ppm/°C | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Zero-Scale Error | -4.8 | 4.8 | LSB | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Zero-Scale Error | -10 | 10 | LSB | VREFP = 10 V, VREFN = 0 V | 3 | ||
| Zero-Scale Error | -20.5 | 20.5 | LSB | VREFP = 5 V, VREFN = 0 V | 3 | ||
| Zero-Scale Error Temperature Coefficient | -0.025 | 0.025 | ppm/°C | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Gain Error | -19 | 19 | ppm FSR | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Gain Error | -35 | 35 | ppm FSR | VREFP = 10 V, VREFN = 0 V | 3 | ||
| Gain Error | -68 | 68 | ppm FSR | VREFP = 5 V, VREFN = 0 V | 3 | ||
| Gain Error Temperature Coefficient | -0.018 | 0.018 | ppm/°C | VREFP = +10 V, VREFN = -10 V | 3 | ||
| Input Bias Current | -20 | -0.63 | 20 | nA | 4 | ||
| Input Bias Current | -4 | -0.63 | 4 | nA | TA = 0°C to 105°C | 4 | |
| Input Current | -1 | 1 | µA | 4 | |||
| High Impedance Leakage Current | -1 | 1 | µA | 4 | |||
| Output Low Voltage | VOL | 0.4 | V | IOVCC = 1.71 V to 5.5 V, sinking 1 mA | 4 | ||
| VREFP Input Range | 5 | V | 4 | ||||
| VREFN Input Range | 0 | V | 4 | ||||
| VDD Supply Voltage | VDD | 7.5 | V | All digital inputs at DGND or IOVCC | 4 | ||
| VSS Supply Voltage | VSS | -2.5 | V | All digital inputs at DGND or IOVCC | 4 | ||
| VCC Supply Voltage | VCC | 2.7 | 5.5 | V | All digital inputs at DGND or IOVCC | 4 | |
| IOVCC Supply Voltage | IOVCC | 1.71 | 5.5 | V | IOVCC ≤ VCC | 4 | |
| Positive Supply Current | IDD | 10.3 | 14 | mA | All digital inputs at DGND or IOVCC | 4 | |
| Negative Supply Current | ISS | -10 | -14 | mA | All digital inputs at DGND or IOVCC | 4 | |
| Digital Supply Current | ICC | 600 | 900 | µA | All digital inputs at DGND or IOVCC | 4 | |
| IOVCC Supply Current | IOICC | 52 | 140 | µA | SDO disabled | 4 | |
| DC Power Supply Rejection Ratio (VDD) | -7.5 | 7.5 | µV/V | ΔVDD ± 10%, VSS = −15 V | 4 | ||
| DC Power Supply Rejection Ratio (VSS) | -1.5 | 1.5 | µV/V | ΔVSS ± 10%, VDD = 15 V | 4 | ||
| VDD to AGND | -0.3 | 34 | V | TA = 25°C | 7 | ||
| VSS to AGND | -34 | 0.3 | V | TA = 25°C | 7 | ||
| VDD to VSS | -0.3 | 34 | V | TA = 25°C | 7 | ||
| VCC to DGND | -0.3 | 7 | V | TA = 25°C | 7 | ||
| DGND to AGND | -0.3 | 0.3 | V | TA = 25°C | 7 | ||
| Operating Temperature Range, TA (Industrial) | TA | -40 | 125 | °C | 7 | ||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Maximum Junction Temperature | TJ max | 150 | °C | 7 | |||
| SCLK cycle time | t1 | 40 | ns | IOVCC = 1.71 V to 3.3 V | 5 | ||
| SCLK cycle time | t1 | 28 | ns | IOVCC = 3.3 V to 5.5 V | 5 | ||
| SCLK cycle time (readback mode) | t1 | 92 | ns | IOVCC = 1.71 V to 3.3 V | 5 | ||
| SCLK cycle time (readback mode) | t1 | 60 | ns | IOVCC = 3.3 V to 5.5 V | 5 | ||
| SCLK high time | t2 | 15 | ns | IOVCC = 1.71 V to 3.3 V | 5 | ||
| SCLK high time | t2 | 10 | ns | IOVCC = 3.3 V to 5.5 V | 5 | ||
| SCLK low time | t3 | 9 | ns | IOVCC = 1.71 V to 3.3 V | 5 | ||
| SCLK low time | t3 | 5 | ns | IOVCC = 3.3 V to 5.5 V | 5 | ||
| Minimum SYNC high time | t6 | 48 | ns | IOVCC = 1.71 V to 3.3 V | 5 | ||
| Minimum SYNC high time | t6 | 40 | ns | IOVCC = 3.3 V to 5.5 V | 5 | ||
| CLR pulse width low | t15 | 50 | ns | 5 | |||
| Output Noise Spectral Density | 8 | nV/√Hz | At 1 kHz, DAC code = midscale | 3 | |||
| Output Voltage Noise | 1.1 | µV p-p | DAC code = midscale, 0.1 Hz to 10 Hz bandwidth | 3 | |||
| Output Voltage Settling Time | 2.5 | µs | 10 V step to 0.02%, using the ADA4898-1 buffer in unity-gain mode | 3 | |||
| Output Voltage Settling Time | 3.5 | µs | 500 code step to ±1 LSB | 3 | |||
| Midscale Glitch Impulse | 14 | nV-sec | VREFP = +10 V, VREFN = -10 V | 3 | |||
| Midscale Glitch Impulse | 3.5 | nV-sec | VREFP = 10 V, VREFN = 0 V | 3 | |||
| Midscale Glitch Impulse | 4 | nV-sec | VREFP = 5 V, VREFN = 0 V | 3 | |||
| DC Output Impedance (Normal Mode) | 3.4 | kΩ | 3 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | ESD (Human Body Model) 1.6 kV Stresses at or above those listed under Absolute Maximum | 7 | |
| contacts | copper | made at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced | 8 |
CAD (KiCad official)
- Symbol:
AD5780ACPZ - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm - 3D model: LFCSP-24(4x5) (KiCad packages3D, STEP)
- 3D model files:
ad5780acpz-etched.step/ad5780acpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5780acpz.step/ad5780acpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (27 pp, sha256
f26d8ca35a30019c, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).