AD5761RBRUZ-RL7

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  "slug": "ad5761rbruz-rl7",
  "title": "AD5761RBRUZ-RL7",
  "brief": "Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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    "data acquisition",
    "ad5761rbruz-rl7",
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  "component": {
    "mpn": "AD5761RBRUZ-RL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
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    "distributor_links": {
      "lcsc": "C515877",
      "digikey": "AD5761RBRUZ-RL7TR-ND",
      "mouser": "584-AD5761RBRUZ-RL7"
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    },
    "pins": [
      {
        "number": "1",
        "name": "ALERT",
        "type": "output",
        "description": "Active-low alarm output that is driven low when the chip temperature exceeds about 150°C or on an output short or power-down, and is also low during power-up, full software reset or hardware reset; a write to the control register returns it high."
      },
      {
        "number": "2",
        "name": "CLEAR",
        "type": "input",
        "description": "Falling-edge clear input that sets the DAC register to zero-scale, mid-scale or full-scale code (user-selectable) and updates the DAC output, with an internal pull-up so it can be left floating; it must be held low for at least 20 ns."
      },
      {
        "number": "3",
        "name": "RESET",
        "type": "input",
        "description": "Active-low reset input that returns the device to its default power-on state, clamps the output to ground and turns off the output buffer, with an internal pull-up so it can be left floating."
      },
      {
        "number": "4",
        "name": "VREFIN/VREFOUT",
        "type": "bidirectional",
        "description": "Internal reference output and external reference input; rated performance is for 2.5 V, the external reference range is 2 V to 3 V, and a 10 nF capacitor is recommended for minimum noise when the internal reference is used."
      },
      {
        "number": "5",
        "name": "AGND",
        "type": "power_in",
        "description": "Ground reference pin for the analog circuitry."
      },
      {
        "number": "6",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative analog supply connection, which may be driven from -16.5 V to 0 V (tied to 0 V for unipolar output ranges) and must be decoupled to AGND."
      },
      {
        "number": "7",
        "name": "VOUT",
        "type": "output",
        "description": "DAC analog output voltage; the output amplifier can drive a 2 kΩ, 1 nF load directly."
      },
      {
        "number": "8",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive analog supply connection, which may be 4.75 V to 30 V for unipolar output ranges and 4.75 V to 16.5 V for bipolar output ranges, and must be decoupled to AGND."
      },
      {
        "number": "9",
        "name": "DNC",
        "type": "unconnected",
        "description": "Do not connect; this pin must not be connected."
      },
      {
        "number": "10",
        "name": "SDO",
        "type": "tri_state",
        "description": "Serial data output used in daisy-chain or readback mode, shifting data out on the SCLK rising edge and valid on the SCLK falling edge; it is three-state when SYNC is high."
      },
      {
        "number": "11",
        "name": "LDAC",
        "type": "input",
        "description": "Load DAC input that updates the DAC register and analog output; when held low permanently the DAC register updates with the input register, and when held high during writes the output updates on the falling edge of LDAC; it has an internal pull-up."
      },
      {
        "number": "12",
        "name": "SDI",
        "type": "input",
        "description": "Serial data input that is sampled on the falling edge of SCLK."
      },
      {
        "number": "13",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame synchronization input for the serial interface; data is clocked in on SCLK falling edges while SYNC is low and latched on the SYNC rising edge."
      },
      {
        "number": "14",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input with data read into the input shift register on the falling edge, operating at up to 50 MHz."
      },
      {
        "number": "15",
        "name": "DVCC",
        "type": "power_in",
        "description": "Digital supply voltage from 1.7 V to 5.5 V that sets the operating voltage of the digital interface."
      },
      {
        "number": "16",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: In the extracted text the description block for VOUT (pin 7) is printed after the pin 8 row, so the ; The pin-configuration drawing (Figure 5) text is garbled and its left-side ordering does not clearly; The datasheet is a Chinese translation of the Analog Devices English datasheet; descriptions were re"
        ],
        "pages_sent": 23,
        "cost_usd": 0.1302,
        "at": "2026-10-19T03:03:21"
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      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "Data Acquisition",
      "Pins": "16"
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          "name": "Digital supply current",
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