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AD5761RBRUZ-RL7
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Analog Devices Digital To Analog Converters (DAC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5761RBRUZ-RL7
Analog Devices · Digital To Analog Converters (DAC) · TSSOP-16
AD5761RBRUZ-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ALERT | output | Active-low alarm output that is driven low when the chip temperature exceeds about 150°C or on an output short or power-down, and is also low during power-up, full software reset or hardware reset; a write to the control register returns it high. |
| 2 | CLEAR | input | Falling-edge clear input that sets the DAC register to zero-scale, mid-scale or full-scale code (user-selectable) and updates the DAC output, with an internal pull-up so it can be left floating; it must be held low for at least 20 ns. |
| 3 | RESET | input | Active-low reset input that returns the device to its default power-on state, clamps the output to ground and turns off the output buffer, with an internal pull-up so it can be left floating. |
| 4 | VREFIN/VREFOUT | bidirectional | Internal reference output and external reference input; rated performance is for 2.5 V, the external reference range is 2 V to 3 V, and a 10 nF capacitor is recommended for minimum noise when the internal reference is used. |
| 5 | AGND | power_in | Ground reference pin for the analog circuitry. |
| 6 | VSS | power_in | Negative analog supply connection, which may be driven from -16.5 V to 0 V (tied to 0 V for unipolar output ranges) and must be decoupled to AGND. |
| 7 | VOUT | output | DAC analog output voltage; the output amplifier can drive a 2 kΩ, 1 nF load directly. |
| 8 | VDD | power_in | Positive analog supply connection, which may be 4.75 V to 30 V for unipolar output ranges and 4.75 V to 16.5 V for bipolar output ranges, and must be decoupled to AGND. |
| 9 | DNC | unconnected | Do not connect; this pin must not be connected. |
| 10 | SDO | tri_state | Serial data output used in daisy-chain or readback mode, shifting data out on the SCLK rising edge and valid on the SCLK falling edge; it is three-state when SYNC is high. |
| 11 | LDAC | input | Load DAC input that updates the DAC register and analog output; when held low permanently the DAC register updates with the input register, and when held high during writes the output updates on the falling edge of LDAC; it has an internal pull-up. |
| 12 | SDI | input | Serial data input that is sampled on the falling edge of SCLK. |
| 13 | SYNC | input | Active-low frame synchronization input for the serial interface; data is clocked in on SCLK falling edges while SYNC is low and latched on the SYNC rising edge. |
| 14 | SCLK | input | Serial clock input with data read into the input shift register on the falling edge, operating at up to 50 MHz. |
| 15 | DVCC | power_in | Digital supply voltage from 1.7 V to 5.5 V that sets the operating voltage of the digital interface. |
| 16 | DGND | power_in | Digital ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL), grade B, 16-bit | INL | -2 | 2 | LSB | Grade B; all ranges except 0 V to 16 V and 0 V to 20 V; VREFIN/VREFOUT = 2.5 V (external and internal) | 3 | |
| Differential nonlinearity (DNL), 16-bit | DNL | -1 | 1 | LSB | 3 | ||
| Zero-scale error | -6 | 6 | mV | All ranges except ±10 V and 0 V to 20 V; external reference | 3 | ||
| Zero-scale error | -10 | 10 | mV | ±10 V and 0 V to 20 V ranges; external reference | 3 | ||
| Zero-scale error | -8 | 8 | mV | ±5 V range; internal reference | 3 | ||
| Zero-scale error | -9 | 9 | mV | 0 V to 20 V range; internal reference | 3 | ||
| Zero-scale error | -13 | 13 | mV | ±10 V range; internal reference | 3 | ||
| Zero-scale error temperature coefficient, unipolar | -5 | 5 | µV/°C | Unipolar ranges; external and internal reference | 3 | ||
| Zero-scale error temperature coefficient, bipolar | -15 | 15 | µV/°C | Bipolar ranges; external and internal reference | 3 | ||
| Bipolar zero-scale error | -5 | 5 | mV | All bipolar ranges except ±10 V | 3 | ||
| Bipolar zero-scale error | -7 | 7 | mV | ±10 V output range | 3 | ||
| Bipolar zero-scale error temperature coefficient | -2 | 2 | µV/°C | ±3 V range; external and internal reference | 3 | ||
| Bipolar zero-scale error temperature coefficient | -5 | 5 | µV/°C | All bipolar ranges except ±3 V; external and internal reference | 3 | ||
| Offset error | -6 | 6 | mV | All ranges except ±10 V and 0 V to 20 V; external reference | 3 | ||
| Offset error | -10 | 10 | mV | ±10 V and 0 V to 20 V ranges; external reference | 3 | ||
| Offset error | -8 | 8 | mV | ±5 V range; internal reference | 3 | ||
| Offset error | -9 | 9 | mV | 0 V to 20 V range; internal reference | 3 | ||
| Offset error | -13 | 13 | mV | ±10 V range; internal reference | 3 | ||
| Offset error temperature coefficient, unipolar | -5 | 5 | µV/°C | Unipolar ranges; external and internal reference | 4 | ||
| Offset error temperature coefficient, bipolar | -15 | 15 | µV/°C | Bipolar ranges; external and internal reference | 4 | ||
| Gain error | -0.1 | 0.1 | % FSR | External reference | 4 | ||
| Gain error | -0.15 | 0.15 | % FSR | Internal reference | 4 | ||
| Gain error temperature coefficient | -1.5 | 1.5 | ppm FSR/°C | External and internal reference | 4 | ||
| Total unadjusted error (TUE) | TUE | -0.1 | 0.1 | % FSR | External reference | 4 | |
| Total unadjusted error (TUE) | TUE | -0.15 | 0.15 | % FSR | Internal reference | 4 | |
| Reference input voltage tolerance (external VREF) | VREF | -1 | 1 | % | Rated performance (2.5 V nominal; 1 V headroom required) | 4 | |
| Reference input current (external VREF) | IREF | -2 | 2 | µA | 4 | ||
| Reference input voltage range (external) | VREF | 2 | 3 | V | 4 | ||
| Internal reference output voltage tolerance | VREFOUT | -3 | 3 | mV | Ambient temperature; nominal 2.5 V | 4 | |
| Internal reference temperature coefficient | 2 | 5 | ppm/°C | 4 | |||
| Output voltage range (±10 V span) | VOUT | -10 | 10 | V | VDD/VSS = ±11 V, ±10 V output range | 4 | |
| Output voltage range (±10 V span, 5% overrange) | VOUT | -10.5 | 10.5 | V | VDD/VSS = ±11 V, ±10 V output range, 5% overrange | 4 | |
| Output voltage temperature coefficient | -3 | 3 | ppm FSR/°C | ±10 V range; external reference | 4 | ||
| Logic input leakage current | -1 | 1 | µA | SDI, SCLK, SYNC | 4 | ||
| SDO high-impedance leakage current | -1 | 1 | µA | SDO high impedance | 5 | ||
| Positive analog supply voltage | VDD | 4.75 | 30 | V | 5 | ||
| Negative analog supply voltage | VSS | -16.5 | 0 | V | 5 | ||
| Digital supply voltage | DVCC | 1.7 | 5.5 | V | 5 | ||
| Positive supply current | IDD | 5.1 | 6.5 | mA | Output unloaded, external reference | 5 | |
| Negative supply current | ISS | 1 | 3 | mA | Output unloaded | 5 | |
| Digital supply current | DICC | 0.005 | 1 | µA | VIH = DVCC, VIL = DGND | 5 | |
| Output voltage settling time (20 V step) | 9 | 12.5 | µs | 20 V step, to 1 LSB, 16-bit resolution | 6 | ||
| Output voltage settling time (10 V step) | 7.5 | 8.5 | µs | 10 V step, to 1 LSB, 16-bit resolution | 6 | ||
| VDD to AGND | VDD | -0.3 | 34 | V | 9 | ||
| VSS to AGND | VSS | -17 | 0.3 | V | 9 | ||
| VDD to VSS | -0.3 | 34 | V | 9 | |||
| DVCC to DGND | DVCC | -0.3 | 7 | V | 9 | ||
| Digital input to DGND | -0.3 | V | 9 | ||||
| Digital output to DGND | -0.3 | V | 9 | ||||
| VREFIN/VREFOUT to DGND | VREFIN/VREFOUT | -0.3 | 7 | V | 9 | ||
| AGND to DGND | -0.3 | 0.3 | V | 9 | |||
| Operating temperature range (industrial) | TA | -40 | 125 | °C | 9 | ||
| Storage temperature range | -65 | 150 | °C | 9 | |||
| Junction temperature | TJ MAX | 150 | °C | 9 | |||
| CLEAR/SDO: SCLK rising edge to SDO valid | t16 | 40 | ns | CL_SDO = 15 pF | 7 | ||
| Thermal resistance, junction to ambient (16-lead TSSOP) | θJA | 113 | °C/W | JEDEC 2S2P test board, still air | 9 | ||
| Thermal resistance, junction to case (16-lead TSSOP) | θJC | 28 | °C/W | 9 |
CAD (KiCad official)
- Symbol:
AD5761RBRUZ-RL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad5761rbruz-rl7-etched.step/ad5761rbruz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5761rbruz-rl7.step/ad5761rbruz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (35 pp, sha256
39496fc3d481ac98, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5761RBRUZ-RL7
**Analog Devices** · Digital To Analog Converters (DAC) · TSSOP-16
AD5761RBRUZ-RL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ALERT | output | Active-low alarm output that is driven low when the chip temperature exceeds about 150°C or on an output short or power-down, and is also low during power-up, full software reset or hardware reset; a write to the control register returns it high. |
| 2 | CLEAR | input | Falling-edge clear input that sets the DAC register to zero-scale, mid-scale or full-scale code (user-selectable) and updates the DAC output, with an internal pull-up so it can be left floating; it must be held low for at least 20 ns. |
| 3 | RESET | input | Active-low reset input that returns the device to its default power-on state, clamps the output to ground and turns off the output buffer, with an internal pull-up so it can be left floating. |
| 4 | VREFIN/VREFOUT | bidirectional | Internal reference output and external reference input; rated performance is for 2.5 V, the external reference range is 2 V to 3 V, and a 10 nF capacitor is recommended for minimum noise when the internal reference is used. |
| 5 | AGND | power_in | Ground reference pin for the analog circuitry. |
| 6 | VSS | power_in | Negative analog supply connection, which may be driven from -16.5 V to 0 V (tied to 0 V for unipolar output ranges) and must be decoupled to AGND. |
| 7 | VOUT | output | DAC analog output voltage; the output amplifier can drive a 2 kΩ, 1 nF load directly. |
| 8 | VDD | power_in | Positive analog supply connection, which may be 4.75 V to 30 V for unipolar output ranges and 4.75 V to 16.5 V for bipolar output ranges, and must be decoupled to AGND. |
| 9 | DNC | unconnected | Do not connect; this pin must not be connected. |
| 10 | SDO | tri_state | Serial data output used in daisy-chain or readback mode, shifting data out on the SCLK rising edge and valid on the SCLK falling edge; it is three-state when SYNC is high. |
| 11 | LDAC | input | Load DAC input that updates the DAC register and analog output; when held low permanently the DAC register updates with the input register, and when held high during writes the output updates on the falling edge of LDAC; it has an internal pull-up. |
| 12 | SDI | input | Serial data input that is sampled on the falling edge of SCLK. |
| 13 | SYNC | input | Active-low frame synchronization input for the serial interface; data is clocked in on SCLK falling edges while SYNC is low and latched on the SYNC rising edge. |
| 14 | SCLK | input | Serial clock input with data read into the input shift register on the falling edge, operating at up to 50 MHz. |
| 15 | DVCC | power_in | Digital supply voltage from 1.7 V to 5.5 V that sets the operating voltage of the digital interface. |
| 16 | DGND | power_in | Digital ground. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL), grade B, 16-bit | INL | -2 | | 2 | LSB | Grade B; all ranges except 0 V to 16 V and 0 V to 20 V; VREFIN/VREFOUT = 2.5 V (external and internal) | 3 |
| Differential nonlinearity (DNL), 16-bit | DNL | -1 | | 1 | LSB | | 3 |
| Zero-scale error | | -6 | | 6 | mV | All ranges except ±10 V and 0 V to 20 V; external reference | 3 |
| Zero-scale error | | -10 | | 10 | mV | ±10 V and 0 V to 20 V ranges; external reference | 3 |
| Zero-scale error | | -8 | | 8 | mV | ±5 V range; internal reference | 3 |
| Zero-scale error | | -9 | | 9 | mV | 0 V to 20 V range; internal reference | 3 |
| Zero-scale error | | -13 | | 13 | mV | ±10 V range; internal reference | 3 |
| Zero-scale error temperature coefficient, unipolar | | -5 | | 5 | µV/°C | Unipolar ranges; external and internal reference | 3 |
| Zero-scale error temperature coefficient, bipolar | | -15 | | 15 | µV/°C | Bipolar ranges; external and internal reference | 3 |
| Bipolar zero-scale error | | -5 | | 5 | mV | All bipolar ranges except ±10 V | 3 |
| Bipolar zero-scale error | | -7 | | 7 | mV | ±10 V output range | 3 |
| Bipolar zero-scale error temperature coefficient | | -2 | | 2 | µV/°C | ±3 V range; external and internal reference | 3 |
| Bipolar zero-scale error temperature coefficient | | -5 | | 5 | µV/°C | All bipolar ranges except ±3 V; external and internal reference | 3 |
| Offset error | | -6 | | 6 | mV | All ranges except ±10 V and 0 V to 20 V; external reference | 3 |
| Offset error | | -10 | | 10 | mV | ±10 V and 0 V to 20 V ranges; external reference | 3 |
| Offset error | | -8 | | 8 | mV | ±5 V range; internal reference | 3 |
| Offset error | | -9 | | 9 | mV | 0 V to 20 V range; internal reference | 3 |
| Offset error | | -13 | | 13 | mV | ±10 V range; internal reference | 3 |
| Offset error temperature coefficient, unipolar | | -5 | | 5 | µV/°C | Unipolar ranges; external and internal reference | 4 |
| Offset error temperature coefficient, bipolar | | -15 | | 15 | µV/°C | Bipolar ranges; external and internal reference | 4 |
| Gain error | | -0.1 | | 0.1 | % FSR | External reference | 4 |
| Gain error | | -0.15 | | 0.15 | % FSR | Internal reference | 4 |
| Gain error temperature coefficient | | -1.5 | | 1.5 | ppm FSR/°C | External and internal reference | 4 |
| Total unadjusted error (TUE) | TUE | -0.1 | | 0.1 | % FSR | External reference | 4 |
| Total unadjusted error (TUE) | TUE | -0.15 | | 0.15 | % FSR | Internal reference | 4 |
| Reference input voltage tolerance (external VREF) | VREF | -1 | | 1 | % | Rated performance (2.5 V nominal; 1 V headroom required) | 4 |
| Reference input current (external VREF) | IREF | -2 | | 2 | µA | | 4 |
| Reference input voltage range (external) | VREF | 2 | | 3 | V | | 4 |
| Internal reference output voltage tolerance | VREFOUT | -3 | | 3 | mV | Ambient temperature; nominal 2.5 V | 4 |
| Internal reference temperature coefficient | | | 2 | 5 | ppm/°C | | 4 |
| Output voltage range (±10 V span) | VOUT | -10 | | 10 | V | VDD/VSS = ±11 V, ±10 V output range | 4 |
| Output voltage range (±10 V span, 5% overrange) | VOUT | -10.5 | | 10.5 | V | VDD/VSS = ±11 V, ±10 V output range, 5% overrange | 4 |
| Output voltage temperature coefficient | | -3 | | 3 | ppm FSR/°C | ±10 V range; external reference | 4 |
| Logic input leakage current | | -1 | | 1 | µA | SDI, SCLK, SYNC | 4 |
| SDO high-impedance leakage current | | -1 | | 1 | µA | SDO high impedance | 5 |
| Positive analog supply voltage | VDD | 4.75 | | 30 | V | | 5 |
| Negative analog supply voltage | VSS | -16.5 | | 0 | V | | 5 |
| Digital supply voltage | DVCC | 1.7 | | 5.5 | V | | 5 |
| Positive supply current | IDD | | 5.1 | 6.5 | mA | Output unloaded, external reference | 5 |
| Negative supply current | ISS | | 1 | 3 | mA | Output unloaded | 5 |
| Digital supply current | DICC | | 0.005 | 1 | µA | VIH = DVCC, VIL = DGND | 5 |
| Output voltage settling time (20 V step) | | | 9 | 12.5 | µs | 20 V step, to 1 LSB, 16-bit resolution | 6 |
| Output voltage settling time (10 V step) | | | 7.5 | 8.5 | µs | 10 V step, to 1 LSB, 16-bit resolution | 6 |
| VDD to AGND | VDD | -0.3 | | 34 | V | | 9 |
| VSS to AGND | VSS | -17 | | 0.3 | V | | 9 |
| VDD to VSS | | -0.3 | | 34 | V | | 9 |
| DVCC to DGND | DVCC | -0.3 | | 7 | V | | 9 |
| Digital input to DGND | | -0.3 | | | V | | 9 |
| Digital output to DGND | | -0.3 | | | V | | 9 |
| VREFIN/VREFOUT to DGND | VREFIN/VREFOUT | -0.3 | | 7 | V | | 9 |
| AGND to DGND | | -0.3 | | 0.3 | V | | 9 |
| Operating temperature range (industrial) | TA | -40 | | 125 | °C | | 9 |
| Storage temperature range | | -65 | | 150 | °C | | 9 |
| Junction temperature | TJ MAX | | | 150 | °C | | 9 |
| CLEAR/SDO: SCLK rising edge to SDO valid | t16 | | | 40 | ns | CL_SDO = 15 pF | 7 |
| Thermal resistance, junction to ambient (16-lead TSSOP) | θJA | | 113 | | °C/W | JEDEC 2S2P test board, still air | 9 |
| Thermal resistance, junction to case (16-lead TSSOP) | θJC | | 28 | | °C/W | | 9 |
## CAD (KiCad official)
- Symbol: `AD5761RBRUZ-RL7`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad5761rbruz-rl7-etched.step` / `ad5761rbruz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5761rbruz-rl7.step` / `ad5761rbruz-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886483508215808) (35 pp, sha256 `39496fc3d481ac98`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5761rbruz-rl7-datasheet.pdf)