AD5700BCPZ-R5 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	XTAL_EN	input	Crystal oscillator enable: low enables the crystal oscillator (external crystal required), high disables it so an external clock or the AD5700-1 internal oscillator provides the clock; used with CLK_CFG0 and CLK_CFG1.
2	CLKOUT	output	Optional clock output from the crystal or internal RC oscillator, and enabling it consumes extra current to drive the load on this pin.
3	CLK_CFG0	input	Clock configuration control pin that selects the clock generation scheme as defined in Table 7.
4	CLK_CFG1	input	Clock configuration control pin that selects the clock generation scheme as defined in Table 7.
5	RESET	input	Active-low digital input: holding it low places the device in power-down mode, and it must be tied to IOVCC if not used.
6	CD	output	Carrier detect digital output that goes high to indicate a valid carrier is detected.
7	TXD	input	Transmit data digital input that provides the data input to the modulator.
8	RTS	input	Request to send digital input: high enables the demodulator and disables the modulator, low enables the modulator and disables the demodulator.
9	DUPLEX	input	High enables full-duplex operation and low disables this feature.
10	RXD	output	UART receive data digital output that carries the demodulator output data.
11	IOVCC	power_in	Digital interface supply from 1.71 V to 5.5 V to which the digital threshold levels are referenced; decouple to ground with low-ESR 10 µF and 0.1 µF capacitors.
12	DGND	power_in	Digital circuitry ground reference, recommended to be connected to AGND for typical operation.
13	REG_CAP	passive	Internal voltage regulator capacitor connection: connect a 1 µF capacitor to ground, and connect this pin to VCC when VCC ≤ 1.98 V.
14	HART_OUT	output	Buffered HART FSK signal output that is DC biased to 0.75 V and must be capacitively coupled to the load.
15	REF	bidirectional	Internal reference voltage output or external 2.5 V reference input; connect a 1 µF capacitor to ground, and VCC must be at least 2.7 V when an external reference is supplied.
16	HART_IN	input	HART FSK signal input for the internal filter, coupled through a 2.2 nF series capacitor, and not connected when an external band-pass filter is used.
17	ADC_IP	input	With the internal filter, connect a 680 pF capacitor to this pin; alternatively it provides direct ADC input when an external band-pass filter is used.
18	VCC	power_in	Power supply input from 1.71 V to 5.5 V, to be decoupled to ground with low-ESR 10 µF and 0.1 µF capacitors.
19	AGND	power_in	Analog circuitry ground reference connection.
20	XTAL2	passive	Connection for an external 3.6864 MHz crystal, which must not be connected when the internal RC oscillator (AD5700-1 only) or an external clock source is used.
21	XTAL1	passive	Connection for an external 3.6864 MHz crystal or external clock source input, which must be tied to ground when the internal RC oscillator (AD5700-1 only) is used.
22	DGND	power_in	Digital circuitry ground reference, recommended to be connected to AGND for typical operation.
23	REF_EN	input	High enables the internal 1.5 V reference and buffer; low disables them and requires a buffered external 2.5 V reference at REF, with VCC greater than 2.7 V.
24	FILTER_SEL	input	High enables the internal band-pass filter with the HART signal applied to HART_IN; low disables it and requires an external band-pass filter with the HART signal applied to ADC_IP.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-24(4x4)
Category	Communication Interface Chip/UART/485/232
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCC power supply voltage	VCC	1.71		5.5	V		3
IOVCC digital interface supply voltage	IOVCC	1.71		5.5	V		3
VCC and IOVCC current consumption, demodulator			86	115	µA	B model, external clock, −40°C to +85°C	3
VCC and IOVCC current consumption, demodulator				179	µA	B model, external clock, −40°C to +125°C	3
VCC and IOVCC current consumption, demodulator with external reference			69	97	µA	B model, external clock, −40°C to +85°C, external reference	3
VCC and IOVCC current consumption, demodulator with external reference				157	µA	B model, external clock, −40°C to +125 °C, external reference	3
VCC and IOVCC current consumption, modulator			124	140	µA	B model, external clock, −40°C to +85°C	3
VCC and IOVCC current consumption, modulator				193	µA	B model, external clock, −40°C to +125°C	3
VCC and IOVCC current consumption, modulator with external reference			73	96	µA	B model, external clock, −40°C to +85°C, external reference	3
VCC and IOVCC current consumption, modulator with external reference				153	µA	B model, external clock, −40°C to +125°C, external reference	3
Crystal oscillator current			33	60	µA	External crystal, 16 pF at XTAL1 and XTAL2	3
Crystal oscillator current			44	71	µA	External crystal, 36 pF at XTAL1 and XTAL2	3
Power-down mode current			16	35	µA	RESET = REF_EN = DGND; internal reference disabled, −40°C to +85°C	3
Power-down mode current				75	µA	RESET = REF_EN = DGND; internal reference disabled, −40°C to +125°C	3
Internal reference voltage		1.47	1.5	1.52	V	REF_EN = IOVCC to enable use of internal reference; VCC = 1.71 V minimum	3
External reference input voltage		2.47	2.5	2.53	V	REF_EN = DGND to enable use of external reference, VCC = 2.7 V minimum	3
External reference input current, demodulator			16	21	µA	Current required by external reference in receive mode	3
External reference input current, modulator			28	33	µA	Current required by external reference in transmit mode	3
External reference input current, power-down			4.6	8.6	µA		3
VIH input high voltage	VIH	0.7			× IOVCC	Printed as 0.7 × IOVCC V	3
VIL input low voltage	VIL			0.3	× IOVCC	Printed as 0.3 × IOVCC V	3
Digital input current		-0.1		0.1	µA		3
Digital input capacitance			5	5	pF	Per pin	3
VOH output high voltage	VOH	0.5			V	Printed as IOVCC − 0.5 V; value is the offset below IOVCC	4
VOL output low voltage	VOL			0.4	V		4
CD assert voltage		85	100	110	mV p-p		4
HART_IN input voltage range		0			V	External reference source; upper limit printed as REF	4
HART_IN input voltage range		0		1.5	V	Internal reference enabled	4
HART_OUT output voltage		459	493	505	mV p-p	AC-coupled (2.2 µF), measured at HART_OUT pin with 160 Ω load (worst-case load)	4
Maximum load resistance at HART_OUT		160			Ω	Worst-case load, ac-coupled with 2.2 µF	4
Transmit impedance at HART_OUT, RTS low				7	Ω	RTS low, at the HART_OUT pin	4
Transmit impedance at HART_OUT, RTS high				70	kΩ	RTS high, at the HART_OUT pin	4
External clock source frequency		3.6496	3.6864	3.7232	MHz		4
Carrier start time	t1			1	Bit time	Time from RTS falling edge to carrier reaching its first peak	5
Carrier stop time	t2			1	Bit time	Time from RTS rising edge to carrier amplitude dropping below the minimum receive amplitude	5
Carrier decay time	t3			1	Bit time	Time from RTS rising edge to carrier amplitude dropping to ac zero	5
Carrier detect on time	t4			6	Bit times	Time from carrier on to CD rising edge	5
Carrier detect off time	t5			6	Bit times	Time from carrier off to CD falling edge	5
Carrier detect on when switching from transmit to receive mode	t6			10	Bit times	In the presence of a constant valid carrier; time from RTS rising edge to CD rising edge	5
Operating temperature range	TA	-40		125	°C	Industrial	6
VCC to GND		-0.3		7	V		6
IOVCC to GND		-0.3		7	V		6
Digital inputs to DGND		-0.3			V	Max is IOVCC + 0.3 V or +7 V, whichever is less	6
Digital output to DGND		-0.3			V	Max is IOVCC + 0.3 V or +7 V, whichever is less	6
HART_OUT to AGND		-0.3		2.5	V		6
HART_IN to AGND		-0.3			V	Max is VCC + 0.3 V or +7 V, whichever is less	6
ADC_IP to AGND		-0.3			V	Max is VCC + 0.3 V or +7 V, whichever is less	6
AGND to DGND		-0.3		0.3	V		6
Storage temperature range		-65		150	°C		6
Junction temperature	TJ MAX			150	°C		6
Carrier detect on, power-up	t7		2.1		ms	Crystal oscillator power-up time; crystal load capacitors = 16 pF	5
Crystal oscillator power-up time	t8		6		ms	Crystal load capacitors = 36 pF	5
Reference power-up time	t10		10		ms		5
Transition time from power-down to normal operating mode	t11		30		µs	External clock source, external reference	5
Load regulation			18		ppm/µA	Tested with 50 µA load	3
Thermal resistance junction-to-ambient	θJA		56		°C/W	24-lead LFCSP; JEDEC 2S2P board with thermal vias; worst-case, soldered in circuit board	6
Thermal resistance junction-to-case	θJC		3		°C/W	24-lead LFCSP	6

CAD (KiCad official)

Symbol: AD5700BCPZ-R5
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
3D model files: ad5700bcpz-r5-etched.step / ad5700bcpz-r5-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5700bcpz-r5.step / ad5700bcpz-r5.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 1cddf01ba605cf47, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5700BCPZ-R5

Verified AD5700BCPZ-R5

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3D Model

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Schematic Symbol

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Datasheet

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