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AD5700-1BCPZ-RL7
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Analog Devices Interface - Specialized, LFCSP-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# AD5700-1BCPZ-RL7++**Analog Devices** · Interface - Specialized · LFCSP-24(4x4)++AD5700-1BCPZ-RL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | XTAL_EN | input | Crystal circuit enable; low level enables external crystal and requires external crystal, high level disables crystal and provides clock from external source or internal oscillator (AD5700-1 only). |+| 2 | CLKOUT | output | Clock output pin; configurable for clock output when using crystal or internal RC oscillator. |+| 3 | CLK_CFG0 | input | Clock configuration control pin; see table 7 for configuration options. |+| 4 | CLK_CFG1 | input | Clock configuration control pin; see table 7 for configuration options. |+| 5 | RESET | input | Low active digital input that places AD5700/AD5700-1 in power-down mode when low; device returns to power-up state when RESET goes high. |+| 6 | CD | output | Carrier detection digital output; high level indicates valid carrier detected. |+| 7 | TXD | input | Transmit data digital input providing data input to the modulator. |+| 8 | RTS | input | Request to send digital input; high level enables demodulator and disables modulator, low level enables modulator and disables demodulator. |+| 9 | DUPLEX | input | Full-duplex enable control; high level enables simultaneous modulator and demodulator operation, low level disables this function. |+| 10 | RXD | output | Receive data UART digital output allowing access to demodulator data output. |+| 11 | IOVCC | power_in | Digital interface power supply accepting 1.71V to 5.5V voltage; digital threshold levels reference this pin and must be decoupled to ground with 10µF and 0.1µF capacitors. |+| 12 | DGND | power_in | Digital circuit ground reference connection; recommended to connect to AGND for typical operation. |+| 13 | REG_CAP | passive | Internal voltage regulator capacitor connection; requires 1µF capacitor connected between this pin and ground. |+| 14 | HART_OUT | output | HART FSK signal output with DC bias at 0.75V and 459-505 mV peak-to-peak amplitude; should be AC coupled to load with capacitor. |+| 15 | REF | passive | Internal 1.5V reference voltage output or external 2.5V reference voltage input; requires 1µF capacitor connected to ground. |+| 16 | HART_IN | input | HART FSK signal input for internal filter configuration; requires AC coupling with 2.2nF series capacitor from HART signal source. |+| 17 | ADC_IP | input | ADC input pin for external bandpass filtered HART signal input or direct ADC connection when using external bandpass filter; requires 680pF capacitor to ground when using internal filter. |+| 18 | VCC | power_in | Power supply input pin accepting 2V to 5.5V voltage; should be decoupled to ground with 10µF and 0.1µF low ESR capacitors. |+| 19 | AGND | power_in | Analog circuit ground reference connection; recommended for typical operation. |+| 20 | XTAL2 | passive | External 3.6864MHz crystal connection or external clock source input; ground this pin if using internal RC oscillator or external CMOS clock. |+| 21 | XTAL1 | passive | External 3.6864MHz crystal connection or external clock source input; ground this pin if using internal RC oscillator. |+| 22 | DGND | power_in | Digital circuit ground reference connection; recommended to connect to AGND for typical operation. |+| 23 | REF_EN | input | Reference voltage source enable control; high level enables internal 1.5V reference source and buffer, low level disables and requires external 2.5V reference at REF pin with VCC minimum 2.7V. |+| 24 | FILTER_SEL | input | Bandpass filter selection control; high level enables internal filter with HART signal applied to HART_IN, low level disables internal filter requiring external bandpass filter network at ADC_IP. |+| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LFCSP-24(4x4) |+| Category | Interface |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `AD5700-1BCPZ-RL7`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`+- 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)+- 3D model files: `ad5700-1bcpz-rl7-etched.step` / `ad5700-1bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5700-1bcpz-rl7.step` / `ad5700-1bcpz-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884589742346240) (24 pp, sha256 `216f1e538d52010b`, retrieved 2026-09-18, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad5700-1bcpz-rl7-datasheet.pdf)
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Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "interface",+ "ad5700-1bcpz-rl7",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ad5700-1bcpz-rl7.kicad_sym",+ "ad5700-1bcpz-rl7.kicad_mod",+ "ad5700-1bcpz-rl7.glb",+ "ad5700-1bcpz-rl7.step",+ "ad5700-1bcpz-rl7.lbr",+ "docs/hero.png",+ "docs/ad5700-1bcpz-rl7-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "AD5700-1BCPZ-RL7",+ "manufacturer": "Analog Devices",+ "package": "LFCSP-24(4x4)",+ "pin_count": 25,+ "category": "Interface",+ "subcategory": "Interface - Specialized",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884589742346240",+ "parts": {+ "symbol": "ad5700-1bcpz-rl7.kicad_sym",+ "footprint": "ad5700-1bcpz-rl7.kicad_mod",+ "model_3d": "ad5700-1bcpz-rl7-etched.glb",+ "model_3d_plain": "ad5700-1bcpz-rl7.glb",+ "model_3d_step": "ad5700-1bcpz-rl7-etched.step",+ "model_3d_step_plain": "ad5700-1bcpz-rl7.step",+ "lbr": "ad5700-1bcpz-rl7.lbr"+ },+ "distributor_links": {+ "lcsc": "C169589"+ },+ "pins": [+ {+ "number": "1",+ "name": "XTAL_EN",+ "type": "input",+ "description": "Crystal circuit enable; low level enables external crystal and requires external crystal, high level disables crystal and provides clock from external source or internal oscillator (AD5700-1 only)."+ },+ {+ "number": "2",+ "name": "CLKOUT",+ "type": "output",+ "description": "Clock output pin; configurable for clock output when using crystal or internal RC oscillator."+ },+ {+ "number": "3",+ "name": "CLK_CFG0",+ "type": "input",+ "description": "Clock configuration control pin; see table 7 for configuration options."+ },+ {+ "number": "4",+ "name": "CLK_CFG1",+ "type": "input",+ "description": "Clock configuration control pin; see table 7 for configuration options."+ },+ {+ "number": "5",+ "name": "RESET",+ "type": "input",+ "description": "Low active digital input that places AD5700/AD5700-1 in power-down mode when low; device returns to power-up state when RESET goes high."+ },+ {+ "number": "6",+ "name": "CD",+ "type": "output",+ "description": "Carrier detection digital output; high level indicates valid carrier detected."+ },+ {+ "number": "7",+ "name": "TXD",+ "type": "input",+ "description": "Transmit data digital input providing data input to the modulator."+ },+ {+ "number": "8",+ "name": "RTS",+ "type": "input",+ "description": "Request to send digital input; high level enables demodulator and disables modulator, low level enables modulator and disables demodulator."+ },+ {+ "number": "9",+ "name": "DUPLEX",+ "type": "input",+ "description": "Full-duplex enable control; high level enables simultaneous modulator and demodulator operation, low level disables this function."+ },+ {+ "number": "10",+ "name": "RXD",+ "type": "output",+ "description": "Receive data UART digital output allowing access to demodulator data output."+ },+ {+ "number": "11",+ "name": "IOVCC",+ "type": "power_in",+ "description": "Digital interface power supply accepting 1.71V to 5.5V voltage; digital threshold levels reference this pin and must be decoupled to ground with 10µF and 0.1µF capacitors."+ },+ {+ "number": "12",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital circuit ground reference connection; recommended to connect to AGND for typical operation."+ },+ {+ "number": "13",+ "name": "REG_CAP",+ "type": "passive",+ "description": "Internal voltage regulator capacitor connection; requires 1µF capacitor connected between this pin and ground."+ },+ {+ "number": "14",+ "name": "HART_OUT",+ "type": "output",+ "description": "HART FSK signal output with DC bias at 0.75V and 459-505 mV peak-to-peak amplitude; should be AC coupled to load with capacitor."+ },+ {+ "number": "15",+ "name": "REF",+ "type": "passive",+ "description": "Internal 1.5V reference voltage output or external 2.5V reference voltage input; requires 1µF capacitor connected to ground."+ },+ {+ "number": "16",+ "name": "HART_IN",+ "type": "input",+ "description": "HART FSK signal input for internal filter configuration; requires AC coupling with 2.2nF series capacitor from HART signal source."+ },+ {+ "number": "17",+ "name": "ADC_IP",+ "type": "input",+ "description": "ADC input pin for external bandpass filtered HART signal input or direct ADC connection when using external bandpass filter; requires 680pF capacitor to ground when using internal filter."+ },+ {+ "number": "18",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply input pin accepting 2V to 5.5V voltage; should be decoupled to ground with 10µF and 0.1µF low ESR capacitors."+ },+ {+ "number": "19",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog circuit ground reference connection; recommended for typical operation."+ },+ {+ "number": "20",+ "name": "XTAL2",+ "type": "passive",+ "description": "External 3.6864MHz crystal connection or external clock source input; ground this pin if using internal RC oscillator or external CMOS clock."+ },+ {+ "number": "21",+ "name": "XTAL1",+ "type": "passive",+ "description": "External 3.6864MHz crystal connection or external clock source input; ground this pin if using internal RC oscillator."+ },+ {+ "number": "22",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital circuit ground reference connection; recommended to connect to AGND for typical operation."+ },+ {+ "number": "23",+ "name": "REF_EN",+ "type": "input",+ "description": "Reference voltage source enable control; high level enables internal 1.5V reference source and buffer, low level disables and requires external 2.5V reference at REF pin with VCC minimum 2.7V."+ },+ {+ "number": "24",+ "name": "FILTER_SEL",+ "type": "input",+ "description": "Bandpass filter selection control; high level enables internal filter with HART signal applied to HART_IN, low level disables internal filter requiring external bandpass filter network at ADC_IP."+ },+ {+ "number": "25",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 24,+ "cost_usd": 0.3423,+ "at": "2026-09-18T05:30:16"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884589742346240",+ "pages": 24,+ "sha256": "216f1e538d52010b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}