# AD5700-1BCPZ-R5

**Analog Devices** · Interface - Specialized · LFCSP-24(4x4)

AD5700-1BCPZ-R5 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | XTAL_EN | input | Crystal oscillator enable: a low state enables the crystal oscillator (external crystal required), and a high state disables it so an external clock or the internal oscillator (AD5700-1 only) provides the clock. |
| 2 | CLKOUT | output | Clock output that can be configured when using the crystal or internal RC oscillator, and enabling it consumes extra current to drive the load on this pin. |
| 3 | CLK_CFG0 | input | Clock configuration control used together with XTAL_EN and CLK_CFG1 to select the clock generation scheme per Table 7 of the datasheet. |
| 4 | CLK_CFG1 | input | Clock configuration control used together with XTAL_EN and CLK_CFG0 to select the clock generation scheme per Table 7 of the datasheet. |
| 5 | RESET | input | Active-low digital input: holding it low places the device in power-down mode, a high returns it to its power-on state, and it should be tied to IOVCC if not used. |
| 6 | CD | output | Carrier detect digital output, where a high indicates a valid carrier is detected. |
| 7 | TXD | input | Transmit data digital input that provides the data stream to the FSK modulator. |
| 8 | RTS | input | Request-to-send digital input: a high state enables the demodulator and disables the modulator, and a low state enables the modulator and disables the demodulator. |
| 9 | DUPLEX | input | A high state enables full-duplex operation and a low state disables this feature. |
| 10 | RXD | output | UART receive data digital output carrying the demodulator data. |
| 11 | IOVCC | power_in | Digital interface supply, 1.71 V to 5.5 V, to which digital threshold levels are referenced; decouple to ground with low ESR 10 µF and 0.1 µF capacitors. |
| 12 | DGND | power_in | Digital circuitry ground reference, recommended to be connected to AGND for typical operation. |
| 13 | REG_CAP | passive | Capacitor connection for the internal voltage regulator: connect a 1 µF capacitor to ground, and connect REG_CAP to VCC when VCC ≤ 1.98 V. |
| 14 | HART_OUT | output | HART FSK signal output, see the FSK Modulator section and Figure 30 of the datasheet for typical connections. |
| 15 | REF | passive | Internal reference voltage output or external 2.5 V reference input, with a 1 µF capacitor to ground, and VCC must be at least 2.7 V when an external reference is supplied. |
| 16 | HART_IN | input | HART FSK signal input for the internal filter, coupled through a 2.2 nF series capacitor, and not to be connected when an external band-pass filter is used. |
| 17 | ADC_IP | input | With the internal band-pass filter, connect 680 pF to this pin; otherwise it is the direct ADC input and an external band-pass filter network must be used. |
| 18 | VCC | power_in | Power supply input, 1.71 V to 5.5 V, decoupled to ground with low ESR 10 µF and 0.1 µF capacitors. |
| 19 | AGND | power_in | Analog circuitry ground reference connection. |
| 20 | XTAL2 | passive | Connection for an external 3.6864 MHz crystal, not to be connected when using the internal RC oscillator (AD5700-1 only) or an external clock source. |
| 21 | XTAL1 | input | Connection for an external 3.6864 MHz crystal or external clock source input, and to be tied to ground when using the internal RC oscillator (AD5700-1 only). |
| 22 | DGND | power_in | Digital circuitry ground reference, recommended to be connected to AGND for typical operation. |
| 23 | REF_EN | input | Reference enable: a high state enables the internal 1.5 V reference and buffer, while a low state disables them and requires a buffered external 2.5 V reference at REF with VCC greater than 2.7 V. |
| 24 | FILTER_SEL | input | Band-pass filter select: a high state enables the internal filter with the HART signal applied to HART_IN, and a low state disables it so an external band-pass filter at ADC_IP is required. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-24(4x4) |
| Category | Interface |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC power supply input voltage | VCC | 1.71 |  | 5.5 | V |  | 3 |
| IOVCC digital interface supply voltage | IOVCC | 1.71 |  | 5.5 | V |  | 3 |
| Operating temperature range | TA | -40 |  | 125 | °C | Industrial | 6 |
| VCC and IOVCC current consumption, demodulator |  |  | 86 | 115 | µA | B model, external clock, −40°C to +85°C | 3 |
| VCC and IOVCC current consumption, demodulator |  |  |  | 179 | µA | B model, external clock, −40°C to +125°C | 3 |
| VCC and IOVCC current consumption, demodulator, external reference |  |  | 69 | 97 | µA | B model, external clock, −40°C to +85°C, external reference | 3 |
| VCC and IOVCC current consumption, demodulator, external reference |  |  |  | 157 | µA | B model, external clock, −40°C to +125 °C, external reference | 3 |
| VCC and IOVCC current consumption, modulator |  |  | 124 | 140 | µA | B model, external clock, −40°C to +85°C | 3 |
| VCC and IOVCC current consumption, modulator |  |  |  | 193 | µA | B model, external clock, −40°C to +125°C | 3 |
| VCC and IOVCC current consumption, modulator, external reference |  |  | 73 | 96 | µA | B model, external clock, −40°C to +85°C, external reference | 3 |
| VCC and IOVCC current consumption, modulator, external reference |  |  |  | 153 | µA | B model, external clock, −40°C to +125°C, external reference | 3 |
| VCC and IOVCC current consumption, crystal oscillator |  |  | 33 | 60 | µA | External crystal, 16 pF at XTAL1 and XTAL2 | 3 |
| VCC and IOVCC current consumption, crystal oscillator |  |  | 44 | 71 | µA | External crystal, 36 pF at XTAL1 and XTAL2 | 3 |
| VCC and IOVCC current consumption, internal oscillator |  |  | 218 | 285 | µA | AD5700-1 only, external crystal not required | 3 |
| Power-down mode current |  |  | 16 | 35 | µA | Internal reference disabled, −40°C to +85°C | 3 |
| Power-down mode current |  |  |  | 75 | µA | Internal reference disabled, −40°C to +125°C | 3 |
| Internal reference voltage |  | 1.47 | 1.5 | 1.52 | V | REF_EN = IOVCC to enable use of internal reference; VCC = 1.71 V minimum | 3 |
| Load regulation |  |  |  | 18 | ppm/µA | Tested with 50 µA load | 3 |
| External reference input voltage |  | 2.47 | 2.5 | 2.53 | V | REF_EN = DGND to enable use of external reference, VCC = 2.7 V minimum | 3 |
| External reference input current, demodulator |  |  | 16 | 21 | µA | Current required by external reference in receive mode | 3 |
| External reference input current, modulator |  |  | 28 | 33 | µA | Current required by external reference in transmit mode | 3 |
| External reference input current, internal oscillator |  |  | 5.5 | 7 | µA | Current required by external reference if using internal oscillator | 3 |
| External reference input current, power-down |  |  | 4.6 | 8.6 | µA |  | 3 |
| Input current |  | -0.1 |  | 0.1 | µA |  | 3 |
| Input capacitance |  |  | 5 | 5 | pF | Per pin | 3 |
| VOL, output low voltage | VOL |  |  | 0.4 | V |  | 4 |
| CD assert |  | 85 | 100 | 110 | mV p-p |  | 4 |
| HART_IN input voltage range, external reference |  | 0 |  |  | V | External reference source | 4 |
| HART_IN input voltage range, internal reference |  | 0 |  | 1.5 | V | Internal reference enabled | 4 |
| HART_OUT output voltage |  | 459 | 493 | 505 | mV p-p | AC-coupled (2.2 µF), measured at HART_OUT pin with 160 Ω load (worst-case load) | 4 |
| Frequency error |  | -0.5 |  | 0.5 | % | Internal oscillator, −40°C to +85°C | 4 |
| Frequency error |  | -1 |  | 1 | % | Internal oscillator, −40°C to +125°C | 4 |
| Internal oscillator frequency |  | 1.2226 | 1.2288 | 1.2349 | MHz | −40°C to +85°C | 4 |
| Internal oscillator frequency |  | 1.2165 | 1.2288 | 1.2411 | MHz | −40°C to +125°C | 4 |
| External clock source frequency |  | 3.6496 | 3.6864 | 3.7232 | MHz |  | 4 |
| Carrier start time (t1) | t1 |  |  | 1 | Bit time | RTS falling edge to carrier reaching first peak | 5 |
| Carrier stop time (t2) | t2 |  |  | 1 | Bit time | RTS rising edge to carrier amplitude dropping below minimum receive amplitude | 5 |
| Carrier decay time (t3) | t3 |  |  | 1 | Bit time | RTS rising edge to carrier amplitude dropping to zero | 5 |
| Carrier detect on (t4) | t4 |  |  | 6 | Bit times | Carrier on to CD rising edge | 5 |
| Carrier detect off (t5) | t5 |  |  | 6 | Bit times | Carrier off to CD falling edge | 5 |
| Carrier detect on, transmit to receive with constant valid carrier (t6) | t6 |  |  | 10 | Bit times | RTS rising edge to CD rising edge | 5 |
| VCC to GND |  | -0.3 |  | 7 | V |  | 6 |
| IOVCC to GND |  | -0.3 |  | 7 | V |  | 6 |
| HART_OUT to AGND |  | -0.3 |  | 2.5 | V |  | 6 |
| AGND to DGND |  | -0.3 |  | 0.3 | V |  | 6 |
| Digital inputs to DGND |  | -0.3 |  |  | V | −0.3 V to IOVCC + 0.3 V or +7 V (whichever is less) | 6 |
| Digital output to DGND |  | -0.3 |  |  | V | −0.3 V to IOVCC + 0.3 V or +7 V (whichever is less) | 6 |
| HART_IN to AGND |  | -0.3 |  |  | V | −0.3 V to VCC + 0.3 V or +7 V (whichever is less) | 6 |
| ADC_IP |  | -0.3 |  |  | V | −0.3 V to VCC + 0.3 V or +7 V (whichever is less) | 6 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 6 |
| Junction temperature | TJ MAX |  |  | 150 | °C |  | 6 |
| Carrier start/mark: mark frequency |  |  | 1200 |  | Hz | Internal oscillator | 4 |
| Space frequency |  |  | 2200 |  | Hz | Internal oscillator | 4 |
| Crystal oscillator power-up time (t7) | t7 |  | 2.1 |  | ms | Crystal load capacitors = 16 pF | 5 |
| Crystal oscillator power-up time (t8) | t8 |  | 6 |  | ms | Crystal load capacitors = 36 pF | 5 |
| Internal oscillator power-up time (t9) | t9 |  | 25 |  | µs |  | 5 |
| Reference power-up time (t10) | t10 |  | 10 |  | ms |  | 5 |
| Transition time from power-down to normal operating mode (t11) | t11 |  | 30 |  | µs | External clock source, external reference | 5 |
| Thermal resistance, junction-to-ambient | θJA |  | 56 |  | °C/W | 24-Lead LFCSP; worst-case, device soldered in circuit board | 6 |
| Thermal resistance, junction-to-case | θJC |  | 3 |  | °C/W | 24-Lead LFCSP | 6 |

## CAD (KiCad official)

- Symbol: `AD5700-1BCPZ-R5`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `ad5700-1bcpz-r5-etched.step` / `ad5700-1bcpz-r5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5700-1bcpz-r5.step` / `ad5700-1bcpz-r5.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884102846025728) (24 pp, sha256 `1cddf01ba605cf47`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5700-1bcpz-r5-datasheet.pdf)