# AD5696RBRUZ

**Analog Devices** · Digital To Analog Converters (DACs) · TSSOP-16

AD5696RBRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference Voltage pin, which is the internal reference output when the internal reference is used and the reference input when an external reference is used, with output as the default. |
| 2 | VOUTB | output | Analog Output Voltage from DAC B, with rail-to-rail output amplifier operation. |
| 3 | VOUTA | output | Analog Output Voltage from DAC A, with rail-to-rail output amplifier operation. |
| 4 | GND | power_in | Ground reference point for all circuitry on the part. |
| 5 | VDD | power_in | Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. |
| 6 | VOUTC | output | Analog Output Voltage from DAC C, with rail-to-rail output amplifier operation. |
| 7 | VOUTD | output | Analog Output Voltage from DAC D, with rail-to-rail output amplifier operation. |
| 8 | SDA | bidirectional | Serial data line, open-drain, that clocks data in or out of the 24-bit input shift register together with SCL and should be pulled to the supply with an external pull-up resistor. |
| 9 | LDAC | input | Load DAC control that can be pulsed low to update any or all DAC registers asynchronously or synchronously, and can also be tied permanently low. |
| 10 | GAIN | input | Span set pin where tying it to GND sets all four DAC outputs to a span of 0 V to VREF and tying it to VLOGIC sets a span of 0 V to 2 × VREF. |
| 11 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 12 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 13 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input register. |
| 14 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 15 | RESET | input | Asynchronous, falling-edge sensitive reset input that updates the input and DAC registers to zero scale or midscale per RSTSEL, and causes LDAC pulses to be ignored while low. |
| 16 | RSTSEL | input | Power-on reset pin that powers all four DACs to zero scale when tied to GND and to midscale when tied to VLOGIC. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `AD5696RBRUZ`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad5696rbruz-etched.step` / `ad5696rbruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5696rbruz.step` / `ad5696rbruz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5696R_5695R_5694R.pdf) (29 pp, sha256 `606267c8d0d475b1`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5696rbruz-datasheet.pdf)