# AD5696RBCPZ-RL7

**Analog Devices** · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5696RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input operated from 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTC | output | Analog output voltage from DAC C; the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D; the output amplifier has rail-to-rail operation. |
| 6 | SDA | bidirectional | Serial data line used with SCL to clock data into or out of the 24-bit input shift register, open-drain and to be pulled to the supply with an external pull-up resistor. |
| 7 | LDAC | input | Pulsing this pin low updates any or all DAC registers from input registers holding new data so all DAC outputs update simultaneously; it can also be tied permanently low. |
| 8 | GAIN | input | Span set pin: tied to GND gives 0 V to VREF output span on all four DACs, tied to VLOGIC gives 0 V to 2 × VREF. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range from 1.62 V to 5.5 V. |
| 10 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 11 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input register. |
| 12 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 13 | RESET | input | Asynchronous, falling-edge-sensitive reset input that loads the input and DAC registers with zero scale or midscale per RSTSEL, and while low all LDAC pulses are ignored. |
| 14 | RSTSEL | input | Power-on reset select: tying this pin to GND powers up all four DACs to zero scale, and tying it to VLOGIC powers up all four DACs to midscale. |
| 15 | VREF | power_in | Common reference pin that is the reference output when using the internal reference and the reference input when using an external reference, defaulting to output. |
| 16 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 17 | EPAD | power_in | Exposed pad that must be tied to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL) | INL | -2 | 1 | 2 | LSB | Gain = 2 | 3 |
| Relative accuracy (INL) | INL | -3 | 1 | 3 | LSB | Gain = 1 | 3 |
| Differential nonlinearity | DNL | -1 |  | 1 | LSB | Guaranteed monotonic by design | 3 |
| Zero-code error |  |  | 0.4 | 1.5 | mV | All zeros loaded to DAC register | 3 |
| Offset error |  | -1.5 | 0.1 | 1.5 | mV |  | 3 |
| Full-scale error |  | -0.1 | 0.01 | 0.1 | % of FSR | All ones loaded to DAC register | 3 |
| Gain error |  | -0.1 | 0.02 | 0.1 | % of FSR |  | 3 |
| Total unadjusted error | TUE | -0.1 | 0.01 | 0.1 | % of FSR |  | 3 |
| Offset error drift |  | -1 |  | 1 | μV/°C |  | 3 |
| Gain temperature coefficient |  | -1 |  | 1 | ppm of FSR/°C |  | 3 |
| DC crosstalk |  | -2 |  | 2 | μV | Due to single channel, full-scale output change | 3 |
| DC crosstalk due to load current change |  | -3 |  | 3 | μV/mA | Due to load current change | 3 |
| DC crosstalk due to powering down |  | -2 |  | 2 | μV | Due to powering down (per channel) | 3 |
| Output voltage range | VOUT | 0 |  |  | V | Gain = 1 | 3 |
| Capacitive load stability | CL |  |  | 2 | nF | RL = ∞ | 3 |
| Capacitive load stability | CL |  |  | 10 | nF | RL = 1 kΩ | 3 |
| Resistive load | RL | 1 |  |  | kΩ |  | 3 |
| Load regulation |  |  |  | 80 | μV/mA | 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA | 3 |
| Short-circuit current |  |  |  | 40 | mA |  | 3 |
| Output voltage (reference) | VREF | 2.4975 |  | 2.5025 | V | At ambient | 4 |
| Reference temperature coefficient | TC |  | 2 | 5 | ppm/°C | See the Terminology section | 4 |
| Output current load capability |  | -5 |  | 5 | mA | VDD ≥ 3 V | 4 |
| Input current |  | -2 |  | 2 | μA | Per pin | 4 |
| Output low voltage | VOL |  |  | 0.4 | V | ISINK = 3 mA | 4 |
| Supply voltage VLOGIC | VLOGIC | 1.62 |  | 5.5 | V |  | 4 |
| Logic supply current | ILOGIC |  |  | 3 | μA |  | 4 |
| Supply voltage VDD | VDD | 2.7 |  | 5.5 | V | Gain = 1 | 4 |
| Supply voltage VDD | VDD |  |  | 5.5 | V | Gain = 2 | 4 |
| Normal mode supply current | IDD |  | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; Internal reference off | 4 |
| Normal mode supply current | IDD |  | 1.1 | 1.3 | mA | Internal reference on, at full scale | 4 |
| All power-down modes supply current | IDD |  | 1 | 4 | μA | −40°C to +85°C | 4 |
| All power-down modes supply current | IDD |  |  | 6 | μA | −40°C to +105°C | 4 |
| Output voltage settling time | tS |  | 5 | 8 | μs | ¼ to ¾ scale settling to ±2 LSB | 5 |
| VDD to GND | VDD | -0.3 |  | 7 | V |  | 7 |
| VLOGIC to GND | VLOGIC | -0.3 |  | 7 | V |  | 7 |
| SDA and SCL to GND |  | -0.3 |  | 7 | V |  | 7 |
| Operating temperature range | TA | -40 |  | 105 | °C |  | 7 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 7 |
| Junction temperature | TJ |  |  | 125 | °C |  | 7 |
| Reflow soldering peak temperature |  |  |  | 260 | °C | Pb free (J-STD-020) | 7 |
| Reference output impedance |  |  | 0.04 |  | Ω |  | 4 |
| Output voltage noise |  |  | 12 |  | μV p-p | 0.1 Hz to 10 Hz | 4 |
| Output voltage noise density |  |  | 240 |  | nV/√Hz | At ambient; f = 10 kHz, CL = 10 nF | 4 |
| Load regulation sourcing |  |  | 20 |  | μV/mA | At ambient | 4 |
| Load regulation sinking |  |  | 40 |  | μV/mA | At ambient | 4 |
| Line regulation |  |  | 100 |  | μV/V | At ambient | 4 |
| Thermal hysteresis |  |  |  | 125 | ppm | First cycle | 4 |
| Thermal hysteresis |  |  |  | 25 | ppm | Additional cycles | 4 |
| Pin capacitance |  |  | 2 |  | pF |  | 4 |
| Floating state output capacitance |  |  | 4 |  | pF |  | 4 |
| Power-up time |  |  | 2.5 |  | μs | Coming out of power-down mode; VDD = 5 V | 3 |
| Load impedance at rails |  |  | 25 |  | Ω | See Figure 30 | 3 |
| Slew rate | SR |  | 0.8 |  | V/µs |  | 5 |
| Thermal impedance, junction to ambient (LFCSP) | θJA |  | 70 |  | °C/W | 0 airflow (4-layer board) | 7 |

## CAD (KiCad official)

- Symbol: `AD5696RBCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5696rbcpz-rl7-etched.step` / `ad5696rbcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5696rbcpz-rl7.step` / `ad5696rbcpz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5696R_5695R_5694R.pdf) (29 pp, sha256 `606267c8d0d475b1`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5696rbcpz-rl7-datasheet.pdf)