component
AD5695RBCPZ-RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD5695RBCPZ-RL7
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)
AD5695RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTC | output | Analog output voltage from DAC C; the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D; the output amplifier has rail-to-rail operation. |
| 6 | SDA | bidirectional | Serial data input/output for the 24-bit input shift register; it is an open-drain line that should be pulled to the supply with an external pull-up resistor. |
| 7 | LDAC | input | Load DAC input that can be pulsed low to update any or all DAC registers simultaneously, or tied permanently low; it can operate asynchronously or synchronously. |
| 8 | GAIN | input | Span set pin: tied to GND sets all four DAC outputs to 0 V to VREF, and tied to VLOGIC sets them to 0 V to 2 × VREF. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 10 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 11 | SCL | input | Serial clock line used in conjunction with SDA to clock data into or out of the 24-bit input register. |
| 12 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 13 | RESET | input | Asynchronous, falling-edge-sensitive reset input that loads the input and DAC registers with zero scale or midscale per RSTSEL, and causes LDAC pulses to be ignored while low. |
| 14 | RSTSEL | input | Power-on reset select pin: tied to GND powers all four DACs up to zero scale, and tied to VLOGIC powers them up to midscale. |
| 15 | VREF | power_in | Common reference pin that is the reference output when using the internal reference (default) and the reference input when using an external reference. |
| 16 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 17 | EPAD | power_in | Exposed pad that must be tied to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5695R B grade | INL | -1 | 1 | LSB | 3 | ||
| Differential Nonlinearity, AD5695R | DNL | -1 | 1 | LSB | Guaranteed monotonic by design | 3 | |
| Zero-Code Error | 0.4 | 1.5 | mV | All zeros loaded to DAC register | 3 | ||
| Offset Error | -1.5 | 0.1 | 1.5 | mV | 3 | ||
| Full-Scale Error | -0.1 | 0.01 | 0.1 | % of FSR | All ones loaded to DAC register | 3 | |
| Gain Error | -0.1 | 0.1 | % of FSR | 3 | |||
| Offset Error Drift | -1 | 1 | μV/°C | 3 | |||
| Gain Temperature Coefficient | -1 | 1 | ppm Of FSR/°C | 3 | |||
| DC Power Supply Rejection Ratio | PSRR | 0.15 | mV/V | DAC code = midscale; VDD = 5 V ± 10% | 3 | ||
| DC Crosstalk, full-scale output change on single channel | -2 | 2 | μV | Due to single channel, full-scale output change | 3 | ||
| DC Crosstalk, load current change | -3 | 3 | μV/mA | Due to load current change | 3 | ||
| DC Crosstalk, powering down | -2 | 2 | μV | Due to powering down (per channel) | 3 | ||
| Capacitive Load Stability | 2 | nF | RL = ∞ | 3 | |||
| Capacitive Load Stability | 10 | nF | RL = 1 kΩ | 3 | |||
| Resistive Load | 1 | kΩ | 3 | ||||
| Load Regulation | 80 | μV/mA | 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA | 3 | |||
| Short-Circuit Current | 40 | mA | VDD = 5 V | 3 | |||
| Power-Up Time | 2.5 | μs | Coming out of power-down mode; VDD = 5 V | 3 | |||
| Output Voltage (internal reference) | 2.4975 | 2.5025 | V | At ambient | 4 | ||
| Reference Temperature Coefficient | 2 | 5 | ppm/°C | See the Terminology section | 4 | ||
| Output Current Load Capability | -5 | 5 | mA | VDD ≥ 3 V | 4 | ||
| Input Current | -2 | 2 | μA | Per pin | 4 | ||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 3 mA | 4 | ||
| Digital Supply Voltage | VLOGIC | 1.62 | 5.5 | V | 4 | ||
| Logic Supply Current | ILOGIC | 3 | μA | 4 | |||
| Supply Voltage | VDD | 2.7 | 5.5 | V | Gain = 1 | 4 | |
| Supply Voltage | VDD | 5.5 | V | Gain = 2 (minimum is VREF + 1.5 V, not numeric as printed) | 4 | ||
| Normal Mode Supply Current | IDD | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; Internal reference off | 4 | |
| Normal Mode Supply Current | IDD | 1.1 | 1.3 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; Internal reference on, at full scale | 4 | |
| All Power-Down Modes Supply Current | IDD | 1 | 4 | μA | −40°C to +85°C | 4 | |
| All Power-Down Modes Supply Current | IDD | 6 | μA | −40°C to +105°C | 4 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 7 | ||
| VLOGIC to GND | VLOGIC | -0.3 | 7 | V | 7 | ||
| VOUT to GND | VOUT | -0.3 | V | Upper limit printed as VDD + 0.3 V | 7 | ||
| VREF to GND | VREF | -0.3 | V | Upper limit printed as VDD + 0.3 V | 7 | ||
| Digital Input Voltage to GND | -0.3 | V | Excluding SDA and SCL; upper limit printed as VLOGIC + 0.3 V | 7 | |||
| SDA and SCL to GND | -0.3 | 7 | V | 7 | |||
| Operating Temperature Range | -40 | 105 | °C | 7 | |||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Junction Temperature | 125 | °C | 7 | ||||
| Reflow Soldering Peak Temperature | 260 | °C | Pb free (J-STD-020) | 7 | |||
| Thermal Impedance, 16-lead LFCSP junction-to-ambient | θJA | 70 | °C/W | 0 airflow, 4-layer board | 7 | ||
| SCL Cycle Time | t1 | 2.5 | μs | 6 | |||
| tHIGH, SCL high time | t2 | 0.6 | μs | 6 | |||
| tLOW, SCL low time | t3 | 1.3 | μs | 6 | |||
| tHD,STA, start/repeated start hold time | t4 | 0.6 | μs | 6 | |||
| tSU,DAT, data setup time | t5 | 100 | ns | 6 | |||
| tHD,DAT, data hold time | t6 | 0 | 0.9 | μs | 6 | ||
| tSU,STA, repeated start setup time | t7 | 0.6 | μs | 6 | |||
| tSU,STO, stop condition setup time | t8 | 0.6 | μs | 6 | |||
| tBUF, bus free time | t9 | 1.3 | μs | 6 | |||
| tR, rise time of SCL and SDA when receiving | t10 | 0 | 300 | ns | 6 | ||
| tF, fall time of SDA and SCL | t11 | 300 | ns | Minimum printed as 20 + 0.1CB | 6 | ||
| LDAC Pulse Width | t12 | 20 | ns | 6 | |||
| SCL Rising Edge to LDAC Rising Edge | t13 | 400 | ns | 6 | |||
| Pulse Width of Suppressed Spike | tSP | 0 | 50 | ns | 6 | ||
| Capacitive Load for Each Bus Line | CB | 400 | pF | 6 |
CAD (KiCad official)
- Symbol:
AD5695RBCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad5695rbcpz-rl7-etched.step/ad5695rbcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5695rbcpz-rl7.step/ad5695rbcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (29 pp, sha256
606267c8d0d475b1, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD5695RBCPZ-RL7
**Analog Devices** · Digital To Analog Converters (DACs) · LFCSP-16(3x3)
AD5695RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the part. |
| 3 | VDD | power_in | Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VOUTC | output | Analog output voltage from DAC C; the output amplifier has rail-to-rail operation. |
| 5 | VOUTD | output | Analog output voltage from DAC D; the output amplifier has rail-to-rail operation. |
| 6 | SDA | bidirectional | Serial data input/output for the 24-bit input shift register; it is an open-drain line that should be pulled to the supply with an external pull-up resistor. |
| 7 | LDAC | input | Load DAC input that can be pulsed low to update any or all DAC registers simultaneously, or tied permanently low; it can operate asynchronously or synchronously. |
| 8 | GAIN | input | Span set pin: tied to GND sets all four DAC outputs to 0 V to VREF, and tied to VLOGIC sets them to 0 V to 2 × VREF. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 10 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 11 | SCL | input | Serial clock line used in conjunction with SDA to clock data into or out of the 24-bit input register. |
| 12 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 13 | RESET | input | Asynchronous, falling-edge-sensitive reset input that loads the input and DAC registers with zero scale or midscale per RSTSEL, and causes LDAC pulses to be ignored while low. |
| 14 | RSTSEL | input | Power-on reset select pin: tied to GND powers all four DACs up to zero scale, and tied to VLOGIC powers them up to midscale. |
| 15 | VREF | power_in | Common reference pin that is the reference output when using the internal reference (default) and the reference input when using an external reference. |
| 16 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 17 | EPAD | power_in | Exposed pad that must be tied to GND. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5695R B grade | INL | -1 | | 1 | LSB | | 3 |
| Differential Nonlinearity, AD5695R | DNL | -1 | | 1 | LSB | Guaranteed monotonic by design | 3 |
| Zero-Code Error | | | 0.4 | 1.5 | mV | All zeros loaded to DAC register | 3 |
| Offset Error | | -1.5 | 0.1 | 1.5 | mV | | 3 |
| Full-Scale Error | | -0.1 | 0.01 | 0.1 | % of FSR | All ones loaded to DAC register | 3 |
| Gain Error | | -0.1 | | 0.1 | % of FSR | | 3 |
| Offset Error Drift | | -1 | | 1 | μV/°C | | 3 |
| Gain Temperature Coefficient | | -1 | | 1 | ppm Of FSR/°C | | 3 |
| DC Power Supply Rejection Ratio | PSRR | | | 0.15 | mV/V | DAC code = midscale; VDD = 5 V ± 10% | 3 |
| DC Crosstalk, full-scale output change on single channel | | -2 | | 2 | μV | Due to single channel, full-scale output change | 3 |
| DC Crosstalk, load current change | | -3 | | 3 | μV/mA | Due to load current change | 3 |
| DC Crosstalk, powering down | | -2 | | 2 | μV | Due to powering down (per channel) | 3 |
| Capacitive Load Stability | | | | 2 | nF | RL = ∞ | 3 |
| Capacitive Load Stability | | | | 10 | nF | RL = 1 kΩ | 3 |
| Resistive Load | | 1 | | | kΩ | | 3 |
| Load Regulation | | | | 80 | μV/mA | 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA | 3 |
| Short-Circuit Current | | | | 40 | mA | VDD = 5 V | 3 |
| Power-Up Time | | | | 2.5 | μs | Coming out of power-down mode; VDD = 5 V | 3 |
| Output Voltage (internal reference) | | 2.4975 | | 2.5025 | V | At ambient | 4 |
| Reference Temperature Coefficient | | | 2 | 5 | ppm/°C | See the Terminology section | 4 |
| Output Current Load Capability | | -5 | | 5 | mA | VDD ≥ 3 V | 4 |
| Input Current | | -2 | | 2 | μA | Per pin | 4 |
| Output Low Voltage | VOL | | | 0.4 | V | ISINK = 3 mA | 4 |
| Digital Supply Voltage | VLOGIC | 1.62 | | 5.5 | V | | 4 |
| Logic Supply Current | ILOGIC | | | 3 | μA | | 4 |
| Supply Voltage | VDD | 2.7 | | 5.5 | V | Gain = 1 | 4 |
| Supply Voltage | VDD | | | 5.5 | V | Gain = 2 (minimum is VREF + 1.5 V, not numeric as printed) | 4 |
| Normal Mode Supply Current | IDD | | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; Internal reference off | 4 |
| Normal Mode Supply Current | IDD | | 1.1 | 1.3 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; Internal reference on, at full scale | 4 |
| All Power-Down Modes Supply Current | IDD | | 1 | 4 | μA | −40°C to +85°C | 4 |
| All Power-Down Modes Supply Current | IDD | | | 6 | μA | −40°C to +105°C | 4 |
| VDD to GND | VDD | -0.3 | | 7 | V | | 7 |
| VLOGIC to GND | VLOGIC | -0.3 | | 7 | V | | 7 |
| VOUT to GND | VOUT | -0.3 | | | V | Upper limit printed as VDD + 0.3 V | 7 |
| VREF to GND | VREF | -0.3 | | | V | Upper limit printed as VDD + 0.3 V | 7 |
| Digital Input Voltage to GND | | -0.3 | | | V | Excluding SDA and SCL; upper limit printed as VLOGIC + 0.3 V | 7 |
| SDA and SCL to GND | | -0.3 | | 7 | V | | 7 |
| Operating Temperature Range | | -40 | | 105 | °C | | 7 |
| Storage Temperature Range | | -65 | | 150 | °C | | 7 |
| Junction Temperature | | | | 125 | °C | | 7 |
| Reflow Soldering Peak Temperature | | | | 260 | °C | Pb free (J-STD-020) | 7 |
| Thermal Impedance, 16-lead LFCSP junction-to-ambient | θJA | | 70 | | °C/W | 0 airflow, 4-layer board | 7 |
| SCL Cycle Time | t1 | 2.5 | | | μs | | 6 |
| tHIGH, SCL high time | t2 | 0.6 | | | μs | | 6 |
| tLOW, SCL low time | t3 | 1.3 | | | μs | | 6 |
| tHD,STA, start/repeated start hold time | t4 | 0.6 | | | μs | | 6 |
| tSU,DAT, data setup time | t5 | 100 | | | ns | | 6 |
| tHD,DAT, data hold time | t6 | 0 | | 0.9 | μs | | 6 |
| tSU,STA, repeated start setup time | t7 | 0.6 | | | μs | | 6 |
| tSU,STO, stop condition setup time | t8 | 0.6 | | | μs | | 6 |
| tBUF, bus free time | t9 | 1.3 | | | μs | | 6 |
| tR, rise time of SCL and SDA when receiving | t10 | 0 | | 300 | ns | | 6 |
| tF, fall time of SDA and SCL | t11 | | | 300 | ns | Minimum printed as 20 + 0.1CB | 6 |
| LDAC Pulse Width | t12 | 20 | | | ns | | 6 |
| SCL Rising Edge to LDAC Rising Edge | t13 | 400 | | | ns | | 6 |
| Pulse Width of Suppressed Spike | tSP | 0 | | 50 | ns | | 6 |
| Capacitive Load for Each Bus Line | CB | | | 400 | pF | | 6 |
## CAD (KiCad official)
- Symbol: `AD5695RBCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5695rbcpz-rl7-etched.step` / `ad5695rbcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5695rbcpz-rl7.step` / `ad5695rbcpz-rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5696R_5695R_5694R.pdf) (29 pp, sha256 `606267c8d0d475b1`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad5695rbcpz-rl7-datasheet.pdf)