component

AD5694RBCPZ-RL7

Public Made by Adom

by adom

Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5694rbcpz-rl7factory-2.0.0extractor-text

Verified AD5694RBCPZ-RL7

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5694RBCPZ-RL7 · LFCSP-16(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 29-page datasheet
  • ✓distributor: lcsc C578277, digikey 505-AD5694RBCPZ-RL7TR-ND, mouser 584-AD5694RBCPZ-R7
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-dtcl19_i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.28)
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5694rbcpz-rl7.kicad_sym✓ ad5694rbcpz-rl7.kicad_mod✓ ad5694rbcpz-rl7.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers ad5694rbcpz-rl7: viewers · Ray 3d ago
ad5694rbcpz-rl7-etched.glb Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7-etched.step ad5694rbcpz-rl7: factory component page (tier=mfr) · Ray 3d ago
ad5694rbcpz-rl7-hero.glb ad5694rbcpz-rl7: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
ad5694rbcpz-rl7-hero.overlay.json Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7.glb Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7.kicad_mod Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7.kicad_sym Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7.lbr Publish 0.1.0 · Ray 3d ago
ad5694rbcpz-rl7.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray 3d ago

AD5694RBCPZ-RL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5694RBCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A with rail-to-rail output amplifier.
2 GND power_in Ground reference point for all circuitry on the part.
3 VDD power_in Power supply input, 2.7 V to 5.5 V, decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTC output Analog output voltage from DAC C with rail-to-rail output amplifier.
5 VOUTD output Analog output voltage from DAC D with rail-to-rail output amplifier.
6 SDA bidirectional I2C serial data line, bidirectional open-drain, to be pulled to the supply with an external pull-up resistor, used with SCL to clock data into or out of the 24-bit input shift register.
7 LDAC input Load DAC input, pulsed low to update any or all DAC registers with new input register data so all outputs update simultaneously, or can be tied permanently low.
8 GAIN input Span set pin: tied to GND gives 0 V to VREF output span, tied to VLOGIC gives 0 V to 2 × VREF for all four DACs.
9 VLOGIC power_in Digital power supply, voltage range 1.62 V to 5.5 V.
10 A0 input Address input that sets the first LSB of the 7-bit slave address.
11 SCL input Serial clock line used with SDA to clock data into or out of the 24-bit input register.
12 A1 input Address input that sets the second LSB of the 7-bit slave address.
13 RESET input Asynchronous falling-edge-sensitive reset input that loads zero scale or midscale per RSTSEL, ignores LDAC pulses while low, and must not be held low at power-up or POR does not initialize correctly.
14 RSTSEL input Power-on reset select: tied to GND powers up all DACs to zero scale, tied to VLOGIC powers up to midscale.
15 VREF power_in Common reference pin that is the reference output when using the internal reference (default) and the reference input when using an external reference.
16 VOUTB output Analog output voltage from DAC B with rail-to-rail output amplifier.
17 EPAD power_in Exposed pad, which must be tied to GND.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL), AD5694R B grade INL -1 0.12 1 LSB 3
Differential Nonlinearity, AD5694R DNL -1 1 LSB Guaranteed monotonic by design 3
Zero-Code Error 0.4 1.5 mV All zeros loaded to DAC register 3
Offset Error -1.5 0.1 1.5 mV 3
Full-Scale Error -0.1 0.01 0.1 % of FSR All ones loaded to DAC register 3
Gain Error -0.1 0.02 0.1 % of FSR 3
Reference Output Voltage 2.4975 2.5025 V At ambient 4
Reference TC 2 5 ppm/°C See the Terminology section 4
Logic Input Current -2 2 μA Per pin 4
Output Low Voltage (SDA) VOL 0.4 V ISINK = 3 mA 4
Reference Output Current Load Capability -5 5 mA VDD ≥ 3 V 4
VLOGIC VLOGIC 1.62 5.5 V 4
VDD VDD 2.7 5.5 V Gain = 1 4
IDD Normal Mode, internal reference off IDD 0.59 0.7 mA VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; internal reference off 4
IDD Normal Mode, internal reference on IDD 1.1 1.3 mA Internal reference on, at full scale 4
IDD All Power-Down Modes IDD 1 4 μA −40°C to +85°C 4
IDD All Power-Down Modes (to 105°C) IDD 6 μA −40°C to +105°C 4
Output Voltage Settling Time, AD5694R 5 7 µs ¼ to ¾ scale settling to ±2 LSB 5
t1 SCL cycle time t1 2.5 μs SCL cycle time 6
t2 SCL high time t2 0.6 μs tHIGH, SCL high time 6
t3 SCL low time t3 1.3 μs tLOW, SCL low time 6
t4 start hold time t4 0.6 μs tHD,STA, start/repeated start condition hold time 6
t5 data setup time t5 100 ns tSU,DAT, data setup time 6
t6 data hold time t6 0 0.9 μs tHD,DAT, data hold time 6
t7 repeated start setup time t7 0.6 μs tSU,STA, setup time for repeated start 6
t8 stop setup time t8 0.6 μs tSU,STO, stop condition setup time 6
t9 bus free time t9 1.3 μs tBUF, bus free time between a stop and a start condition 6
t10 rise time t10 0 300 ns tR, rise time of SCL and SDA when receiving 6
t11 fall time t11 300 ns tF, fall time of SDA and SCL when transmitting/receiving (min 20 + 0.1CB) 6
t12 LDAC pulse width t12 20 ns LDAC pulse width 6
t13 SCL rising to LDAC rising t13 400 ns SCL rising edge to LDAC rising edge 6
tSP suppressed spike pulse width tSP 0 50 ns Pulse width of suppressed spike 6
Bus line capacitive load CB 400 pF Capacitive load for each bus line 6
VDD to GND VDD -0.3 7 V TA = 25°C 7
VLOGIC to GND VLOGIC -0.3 7 V TA = 25°C 7
VREF to GND VREF -0.3 V −0.3 V to VDD + 0.3 V 7
Digital Input Voltage to GND -0.3 V −0.3 V to VLOGIC + 0.3 V, excluding SDA and SCL 7
SDA and SCL to GND -0.3 7 V 7
Operating Temperature Range -40 105 °C 7
Storage Temperature Range -65 150 °C 7
Junction Temperature TJ 125 °C 7
Reflow Soldering Peak Temperature, Pb Free 260 °C J-STD-020 7
16-Lead LFCSP θJA Thermal Impedance θJA 70 °C/W 0 Airflow (4-Layer Board) 7
Offset Error Drift 1 μV/°C printed ±1 3
Gain Temperature Coefficient 1 ppm Of FSR/°C printed ±1 3
DC Power Supply Rejection Ratio 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% 3
Load Regulation 80 μV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ IOUT ≤ 30 mA 3
Short-Circuit Current 40 mA VDD = 5 V 3
Load Impedance at Rails 25 Ω See Figure 30 3
Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V 3
ILOGIC ILOGIC 3 µA 4
Reference Thermal Hysteresis 125 ppm First cycle 4

CAD (KiCad official)

  • Symbol: AD5694RBCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ad5694rbcpz-rl7-etched.step / ad5694rbcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5694rbcpz-rl7.step / ad5694rbcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (29 pp, sha256 606267c8d0d475b1, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF