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AD5694BCPZ-RL7

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Analog Devices Digital To Analog Converters (DACs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5694bcpz-rl7factory-2.0.0extractor-text

Verified AD5694BCPZ-RL7

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5694BCPZ-RL7 · LFCSP-16(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C650139, digikey 505-AD5694BCPZ-RL7TR-ND, mouser 584-AD5694BCPZ-R7
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-y7sr1jdq/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5694bcpz-rl7.kicad_sym✓ ad5694bcpz-rl7.kicad_mod✓ ad5694bcpz-rl7.step
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Ray Publish 0.1.0 f03bd24 17h ago

AD5694BCPZ-RL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5694BCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTA output Analog output voltage from DAC A, with a rail-to-rail output amplifier.
2 GND power_in Ground reference point for all circuitry on the part.
3 VDD power_in Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VOUTC output Analog output voltage from DAC C, with a rail-to-rail output amplifier.
5 VOUTD output Analog output voltage from DAC D, with a rail-to-rail output amplifier.
6 SDA bidirectional Open-drain serial data line for the 24-bit input shift register, to be pulled to the supply with an external pull-up resistor.
7 LDAC input Pulsing low updates any or all DAC registers with new input-register data simultaneously, and the pin may be tied permanently low.
8 GAIN input Gain select: tied to GND sets all DAC spans to 0 V to VREF, and tied to VLOGIC sets all spans to 0 V to 2 × VREF.
9 VLOGIC power_in Digital power supply with a voltage range from 1.62 V to 5.5 V.
10 A0 input Address input that sets the first LSB of the 7-bit slave address.
11 SCL input Serial clock line used with SDA to clock data into or out of the 24-bit input shift register.
12 A1 input Address input that sets the second LSB of the 7-bit slave address.
13 RESET input Falling-edge-sensitive asynchronous reset that loads the input and DAC registers with zero scale or midscale per RSTSEL, and causes LDAC pulses to be ignored while low.
14 RSTSEL input Power-on reset select: tied to GND powers all four DACs up to zero scale, and tied to VLOGIC powers them up to midscale.
15 VREF power_in Reference input voltage for the DACs.
16 VOUTB output Analog output voltage from DAC B, with a rail-to-rail output amplifier.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category ADC/DAC/Data Conversion
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy INL -1 0.12 1 LSB 4
Differential Nonlinearity DNL -1 1 LSB Guaranteed monotonic by design 4
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register 4
Offset Error -1.5 0.1 1.5 mV 4
Full-Scale Error -0.1 0.01 0.1 % of FSR All 1s loaded to DAC register 4
Gain Error -0.1 0.02 0.1 % of FSR 4
Total Unadjusted Error TUE -0.1 0.01 0.1 % of FSR Gain = 2 4
Total Unadjusted Error TUE -0.2 0.2 % of FSR Gain = 1 4
Offset Error Drift -1 1 µV/°C 4
Gain Temperature Coefficient -1 1 ppm Of FSR/°C 4
DC Power Supply Rejection Ratio 0.15 mV/V DAC code = midscale; VDD = 5 V ± 10% 4
Capacitive Load Stability 2 nF RL = ∞ 4
Capacitive Load Stability 10 nF RL = 1 kΩ 4
Resistive Load 1 kΩ 4
Load Regulation 80 µV/mA DAC code = midscale; 5 V ± 10%; −30 mA ≤ IOUT ≤ +30 mA 4
Short-Circuit Current 40 mA 4
Load Impedance at Rails 25 Ω See Figure 20 4
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V 4
Reference Current 90 µA VREF = VDD = 5.5 V, gain = 1 4
Reference Current 180 µA VREF = VDD = 5.5 V, gain = 2 4
Reference Input Impedance 16 kΩ Gain = 2 4
Reference Input Impedance 32 kΩ Gain = 1 4
Input Current -2 2 µA Per pin 4
Pin Capacitance 2 pF 5
Output Low Voltage VOL 0.4 V ISINK = 3 mA 5
Floating State Output Capacitance 4 pF 5
VLOGIC VLOGIC 1.62 5.5 V 5
ILOGIC ILOGIC 3 µA 5
VDD VDD 2.7 5.5 V Gain = 1 5
Normal Mode IDD IDD 0.59 0.7 mA VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V; interface inactive, all DACs active 5
All Power-Down Modes IDD IDD 1 4 µA −40°C to +85°C 5
All Power-Down Modes IDD IDD 6 µA −40°C to +105°C 5
Output Voltage Settling Time AD5694 5 7 µs ¼ to ¾ scale settling to ±2 LSB 5
Slew Rate 0.8 V/µs 5
Multiplying Bandwidth 500 kHz 5
VDD to GND VDD -0.3 7 V 8
VLOGIC to GND VLOGIC -0.3 7 V 8
SDA and SCL to GND -0.3 7 V 8
Operating Temperature Range -40 105 °C 8
Storage Temperature Range -65 150 °C 8
Junction Temperature 125 °C 8
Reflow Soldering Peak Temperature 260 °C Pb Free (J-STD-020) 8
Thermal Resistance 16-Lead LFCSP θJA 70 °C/W JEDEC 4-layer board, zero airflow 8
SCL cycle time t1 2.5 µs 6
tHIGH, SCL high time t2 0.6 µs 6
tLOW, SCL low time t3 1.3 µs 6
tHD,STA, start/repeated start hold time t4 0.6 µs 6
tSU,DAT, data setup time t5 100 ns 6
tHD,DAT, data hold time t6 0 0.9 µs 6
tSU,STA, repeated start setup time t7 0.6 µs 6
tSU,STO, stop condition setup time t8 0.6 µs 6
tBUF, bus free time between stop and start t9 1.3 µs 6
tR, rise time of SCL and SDA when receiving t10 0 300 ns 6
LDAC pulse width t12 20 ns 6
SCL rising edge to LDAC rising edge t13 400 ns 6
Pulse width of suppressed spike tSP 0 50 ns 6

CAD (KiCad official)

  • Symbol: AD5694BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: ad5694bcpz-rl7-etched.step / ad5694bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5694bcpz-rl7.step / ad5694bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 6511b9dc603ebc4c, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF