# AD5687BCPZ-RL7

**Analog Devices** · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5687BCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUTA | output | Analog output voltage from DAC A; the output amplifier has rail-to-rail operation. |
| 2 | GND | power_in | Ground reference point for all circuitry on the device. |
| 3 | VDD | power_in | Power supply input operable from 2.7 V to 5.5 V; decouple with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | NC | unconnected | No connect; do not connect to this pin. |
| 5 | VOUTB | output | Analog output voltage from DAC B; the output amplifier has rail-to-rail operation. |
| 6 | SDO | output | Serial data output used for daisy-chaining or readback; data is transferred on the SCLK rising edge and is valid on the falling edge. |
| 7 | LDAC | input | Asynchronous or synchronous DAC update control; pulsing low updates DAC registers that have new input data, and the pin can be tied permanently low. |
| 8 | GAIN | input | Gain select; tying to GND gives a 0 V to VREF output span, and tying to VLOGIC gives a 0 V to 2 × VREF span. |
| 9 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 10 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge at rates up to 50 MHz. |
| 11 | SYNC | input | Active-low frame synchronization input; when it goes low, data is transferred in on the falling edges of the next 24 clocks. |
| 12 | SDIN | input | Serial data input to a 24-bit input shift register, clocked in on the falling edge of SCLK. |
| 13 | RESET | input | Asynchronous reset input, falling-edge sensitive; when low, LDAC pulses are ignored, and activation loads the input and DAC registers with zero scale or midscale per RSTSEL. |
| 14 | RSTSEL | input | Power-on reset select; tying to GND powers both DACs up to zero scale, and tying to VLOGIC powers them up to midscale. |
| 15 | VREF | power_in | Reference input voltage for the DACs. |
| 16 | NC | unconnected | No connect; do not connect to this pin. |
| 17 | EPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5687 12-bit |  | -1 | 0.12 | 1 | LSB |  | 3 |
| Differential Nonlinearity, AD5687 |  | -1 |  | 1 | LSB | Guaranteed monotonic by design | 3 |
| Offset Error |  | -1.5 | 0.1 | 1.5 | mV |  | 3 |
| Full-Scale Error |  | -0.1 | 0.01 | 0.1 | % of FSR | All 1s loaded to DAC register | 3 |
| Gain Error |  | -0.1 | 0.02 | 0.1 | % of FSR |  | 3 |
| Zero-Code Error |  |  | 0.4 | 1.5 | mV | All 0s loaded to DAC register | 3 |
| Offset Error Drift |  | -1 |  | 1 | µV/°C |  | 3 |
| Gain Temperature Coefficient |  | -1 |  | 1 | ppm Of FSR/°C |  | 3 |
| DC Crosstalk due to single-channel full-scale output change |  | -2 |  | 2 | µV | Due to single-channel, full-scale output change | 3 |
| DC Crosstalk due to load current change |  | -3 |  | 3 | µV/mA | Due to load current change | 3 |
| DC Crosstalk due to powering down (per channel) |  | -2 |  | 2 | µV | Due to powering down (per channel) | 3 |
| Output Voltage Range, gain = 1 (upper limit VREF, not numeric) |  | 0 |  |  | V | Gain = 1 | 3 |
| Output Voltage Range, gain = 2 (upper limit 2 × VREF, not numeric) |  | 0 |  |  | V | Gain = 2; see Figure 24 | 3 |
| Capacitive Load Stability |  |  |  | 2 | nF | RL = ∞ | 3 |
| Capacitive Load Stability |  |  |  | 10 | nF | RL = 1 kΩ | 3 |
| Reference Input Range, gain = 1 (upper limit VDD, not numeric) | VREF | 1 |  |  | V | Gain = 1 | 3 |
| Reference Input Range, gain = 2 (upper limit VDD/2, not numeric) | VREF | 1 |  |  | V | Gain = 2 | 3 |
| Input Current |  | -2 |  | 2 | µA | Per pin | 3 |
| Output Low Voltage (SDO) | VOL |  |  | 0.4 | V | ISINK = 200 μA | 4 |
| VLOGIC Digital Supply Voltage | VLOGIC | 1.62 |  | 5.5 | V |  | 4 |
| VDD Power Supply, gain = 1 | VDD | 2.7 |  | 5.5 | V | Gain = 1 | 4 |
| VDD Power Supply, gain = 2 (minimum VREF + 1.5 V, not numeric) | VDD |  |  | 5.5 | V | Gain = 2 | 4 |
| Normal Mode Supply Current | IDD |  | 0.59 | 0.7 | mA | VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 4 |
| All Power-Down Modes Supply Current | IDD |  | 1 | 4 | µA | −40°C to +85°C | 4 |
| All Power-Down Modes Supply Current | IDD |  |  | 6 | µA | −40°C to +105°C | 4 |
| Output Voltage Settling Time, AD5687 |  |  | 5 | 7 | µs | ¼ to ¾ scale settling to ±2 LSB | 4 |
| SCLK Cycle Time | t1 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK High Time | t2 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK Low Time | t3 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNCE to SCLK Falling Edge Setup Time | t4 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Data Setup Time | t5 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Data Hold Time | t6 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK Falling Edge to SYNCE Rising Edge | t7 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Minimum SYNCE High Time | t8 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNCE Rising Edge to SYNCE Rising Edge (DAC Register Updates) | t9 | 830 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNCE Falling Edge to SCLK Fall Ignore | t10 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| LDACE Pulse Width Low | t11 | 15 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNCE Rising Edge to LDACE Rising Edge | t12 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNCE Rising Edge to LDACE Falling Edge | t13 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| LDACE Falling Edge to SYNCE Rising Edge | t14 | 800 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Minimum Pulse Width Low | t15 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Pulse Activation Time | t16 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Power-Up Time |  |  |  | 4.5 | µs |  | 5 |
| VDD to GND | VDD | -0.3 |  | 7 | V |  | 8 |
| VLOGIC to GND | VLOGIC | -0.3 |  | 7 | V |  | 8 |
| VOUT to GND (upper limit VDD + 0.3 V, not numeric) | VOUT | -0.3 |  |  | V |  | 8 |
| VREF to GND (upper limit VDD + 0.3 V, not numeric) | VREF | -0.3 |  |  | V |  | 8 |
| Digital Input Voltage to GND (upper limit VLOGIC + 0.3 V, not numeric) |  | -0.3 |  |  | V |  | 8 |
| Operating Temperature Range |  | -40 |  | 105 | °C |  | 8 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 8 |
| Junction Temperature |  |  |  | 125 | °C |  | 8 |
| 16-Lead LFCSP θJA Thermal Impedance | θJA |  | 70 |  | °C/W | 0 Airflow (4-Layer Board) | 8 |

## CAD (KiCad official)

- Symbol: `AD5687BCPZ-RL7`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `ad5687bcpz-rl7-etched.step` / `ad5687bcpz-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5687bcpz-rl7.step` / `ad5687bcpz-rl7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5689_5687.pdf) (24 pp, sha256 `af1dd912a1b64dd7`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5687bcpz-rl7-datasheet.pdf)