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AD5686RACPZ-RL7

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-16(3x3)

AD5686RACPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUTA	output	Analog output voltage from DAC A; the output amplifier has rail-to-rail operation.
2	GND	power_in	Ground reference point for all circuitry on the part.
3	VDD	power_in	Power supply input operable from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4	VOUTC	output	Analog output voltage from DAC C; the output amplifier has rail-to-rail operation.
5	VOUTD	output	Analog output voltage from DAC D; the output amplifier has rail-to-rail operation.
6	SDO	output	Serial data output for daisy-chaining or readback; data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
7	LDAC	input	Load DAC input that, when pulsed low, updates any or all DAC registers that have new input data; it can also be tied permanently low.
8	GAIN	input	Span set pin: tied to GND sets all DAC outputs to 0 V to VREF, and tied to VLOGIC sets all DAC outputs to 0 V to 2 x VREF.
9	VLOGIC	power_in	Digital power supply whose voltage ranges from 1.8 V to 5.5 V.
10	SCLK	input	Serial clock input; data is clocked into the input shift register on the falling edge at rates of up to 50 MHz.
11	SYNC	input	Active-low frame synchronization input; when SYNC goes low, data is transferred in on the falling edges of the next 24 clocks.
12	SDIN	input	Serial data input to a 24-bit input shift register, clocked in on the falling edge of the serial clock.
13	RESET	input	Asynchronous, falling-edge-sensitive reset input that loads zero scale or midscale per RSTSEL; LDAC pulses are ignored while RESET is low.
14	RSTSEL	input	Power-on reset select: tying to GND powers up all four DACs to zero scale, and tying to VLOGIC powers them up to midscale.
15	VREF	power_in	Common reference pin that is the reference output when using the internal reference (default) and the reference input when using an external reference.
16	VOUTB	output	Analog output voltage from DAC B; the output amplifier has rail-to-rail operation.
17	EPAD	power_in	Exposed pad that must be tied to GND.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-16(3x3)
Category	ADC/DAC/Data Conversion
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (AD5686R, gain = 2)	INL	-8	2	8	LSB	Gain = 2	3
Zero-Code Error			0.4	4	mV	All zeros loaded to DAC register	3
Offset Error		-4	0.1	4	mV		3
Full-Scale Error		-0.2	0.01	0.2	% of FSR	All ones loaded to DAC register	3
Gain Error		-0.2		0.2	% of FSR		3
Reference Output Voltage		2.4975		2.5025	V	At ambient	3
Reference TC			5	20	ppm/°C	See the Terminology section	3
Output Impedance			0.04		Ω		4
Output Voltage Noise			12		µV p-p	0.1 Hz to 10 Hz	4
Output Current Load Capability		-5		5	mA	VDD ≥ 3 V	4
Input Current	IIN	-2		2	µA	Per pin	4
Input Low Voltage	VINL			0.3	× VLOGIC		4
Input High Voltage	VINH	0.7			× VLOGIC		4
Output Low Voltage	VOL			0.4	V	ISINK = 200 μA	4
Logic Supply Voltage	VLOGIC	1.62		5.5	V		4
Logic Supply Current	ILOGIC			3	µA		4
Supply Voltage	VDD	2.7		5.5	V	Gain = 1	4
Normal Mode Supply Current	IDD		0.59	0.7	mA	Internal reference off; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V	4
Normal Mode Supply Current	IDD		1.1	1.3	mA	Internal reference on, at full scale	4
All Power-Down Modes Supply Current	IDD	1		4	µA	−40°C to +85°C	4
All Power-Down Modes Supply Current	IDD			6	µA	−40°C to +105°C	4
SCLK Cycle Time	t1	20			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	5
SCLK High Time	t2	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	5
SCLK Low Time	t3	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	5
Supply Voltage (VDD to GND)	VDD	-0.3		7	V		8
VLOGIC to GND	VLOGIC	-0.3		7	V		8
Operating Temperature Range		-40		105	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature				125	°C		8
16-Lead LFCSP Thermal Impedance θJA	θJA		70		°C/W	0 Airflow, 4-Layer Board	8

CAD (KiCad official)

Symbol: AD5686RACPZ-RL7
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
3D model files: ad5686racpz-rl7-etched.step / ad5686racpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5686racpz-rl7.step / ad5686racpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (29 pp, sha256 16c7cb655e87649e, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF