# AD5685RBRUZ

**Analog Devices** · Digital To Analog Converters (DACs) · TSSOP-16

AD5685RBRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Reference voltage pin: it is the reference output when the internal reference is used (the default), or the reference input when an external reference is used. |
| 2 | VOUTB | output | Analog output voltage from DAC B, with a rail-to-rail output amplifier. |
| 3 | VOUTA | output | Analog output voltage from DAC A, with a rail-to-rail output amplifier. |
| 4 | GND | power_in | Ground reference point for all circuitry on the part. |
| 5 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 6 | VOUTC | output | Analog output voltage from DAC C, with a rail-to-rail output amplifier. |
| 7 | VOUTD | output | Analog output voltage from DAC D, with a rail-to-rail output amplifier. |
| 8 | SDO | output | Serial data output used to daisy-chain devices or for readback, transferred on the rising edge of SCLK and valid on the falling edge. |
| 9 | LDAC | input | Pulsing this pin low updates any or all DAC registers that hold new input data, allowing simultaneous DAC output updates; it can also be tied permanently low. |
| 10 | GAIN | input | Span set pin: tying it to GND gives a 0 V to VREF output span on all four DACs, and tying it to VLOGIC gives 0 V to 2 × VREF. |
| 11 | VLOGIC | power_in | Digital power supply with a voltage range of 1.8 V to 5.5 V. |
| 12 | SCLK | input | Serial clock input that clocks data into the input shift register on the falling edge, at rates of up to 50 MHz. |
| 13 | SYNC | input | Active-low frame synchronization input; when it goes low, data is transferred in on the falling edges of the next 24 clocks. |
| 14 | SDIN | input | Serial data input to the 24-bit input shift register, clocked in on the falling edge of the serial clock. |
| 15 | RESET | input | Falling-edge-sensitive asynchronous reset input that sets the DAC outputs to zero scale or midscale per RSTSEL, and all LDAC pulses are ignored while it is low. |
| 16 | RSTSEL | input | Power-on reset select: tying it to GND powers up all four DACs to zero scale, and tying it to VLOGIC powers up all four DACs to midscale. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL), AD5685R, B grade |  | -1 | 0.5 | 1 | LSB |  | 3 |
| Differential Nonlinearity, AD5685R, B grade |  | -1 |  | 1 | LSB | Guaranteed monotonic by design | 3 |
| Zero-Code Error, B grade |  |  | 0.4 | 1.5 | mV | All zeros loaded to DAC register | 3 |
| Offset Error, B grade |  | -1.5 | 0.1 | 1.5 | mV |  | 3 |
| Full-Scale Error, B grade |  | -0.1 | 0.01 | 0.1 | % of FSR | All ones loaded to DAC register | 3 |
| Gain Error, B grade |  | -0.1 | 0.02 | 0.1 | % of FSR |  | 3 |
| Total Unadjusted Error, B grade, TSSOP |  | -0.1 | 0.01 | 0.1 | % of FSR | External reference; gain = 2; TSSOP | 3 |
| Total Unadjusted Error, B grade, TSSOP |  | -0.2 |  | 0.2 | % of FSR | Internal reference; gain = 1; TSSOP | 3 |
| Offset Error Drift, B grade |  | -1 |  | 1 | µV/°C |  | 3 |
| Gain Temperature Coefficient, B grade |  | -1 |  | 1 | ppm Of FSR/°C |  | 3 |
| DC Crosstalk, full-scale output change of single channel |  | -2 |  | 2 | µV | Due to single channel, full-scale output change | 3 |
| DC Crosstalk, load current change |  | -3 |  | 3 | µV/mA | Due to load current change | 3 |
| DC Crosstalk, powering down (per channel) |  | -2 |  | 2 | µV | Due to powering down (per channel) | 3 |
| Output Voltage Range, gain = 1 (max = VREF) | VOUT | 0 |  |  | V | Gain = 1 | 3 |
| Output Voltage Range, gain = 2 (max = 2 × VREF) | VOUT | 0 |  |  | V | Gain = 2, see Figure 33 | 3 |
| Capacitive Load Stability |  |  |  | 2 | nF | RL = ∞ | 3 |
| Capacitive Load Stability |  |  |  | 10 | nF | RL = 1 kΩ | 3 |
| Resistive Load (minimum) |  | 1 |  |  | kΩ |  | 3 |
| Output Current Load Capability |  | -5 |  | 5 | mA | VDD ≥ 3 V | 4 |
| Reference Output Voltage |  | 2.4975 |  | 2.5025 | V | At ambient | 3 |
| Reference Temperature Coefficient, B grade |  |  | 2 | 5 | ppm/°C | See the Terminology section | 3 |
| Logic Input Current |  | -2 |  | 2 | µA | Per pin | 4 |
| Logic Output Low Voltage (SDO) | VOL |  |  | 0.4 | V | ISINK = 200 μA | 4 |
| Digital Power Supply Voltage (VLOGIC) | VLOGIC | 1.62 |  | 5.5 | V |  | 3 |
| Logic Supply Current | ILOGIC |  |  | 3 | µA |  | 3 |
| Supply Voltage (VDD) | VDD | 2.7 |  | 5.5 | V | Gain = 1 | 3 |
| Supply Voltage (VDD), min = VREF + 1.5 V | VDD |  |  | 5.5 | V | Gain = 2 | 3 |
| Normal Mode Supply Current | IDD |  | 0.59 | 0.7 | mA | Internal reference off; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 3 |
| Normal Mode Supply Current, internal reference on | IDD |  | 1.1 | 1.3 | mA | Internal reference on, at full scale; VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V | 3 |
| Power-Down Mode Supply Current | IDD |  | 1 | 4 | µA | −40°C to +85°C | 3 |
| Power-Down Mode Supply Current | IDD |  |  | 6 | µA | −40°C to +105°C | 3 |
| Output Voltage Settling Time, AD5685R |  |  | 5 | 8 | µs | ¼ to ¾ scale settling to ±2 LSB | 5 |
| SCLK Cycle Time | t1 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK High Time | t2 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK Low Time | t3 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNC to SCLK Falling Edge Setup Time | t4 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Data Setup Time | t5 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Data Hold Time | t6 | 5 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SCLK Falling Edge to SYNC Rising Edge | t7 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Minimum SYNC High Time | t8 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNC Rising Edge to SYNC Rising Edge (DAC Register Updates) | t9 | 830 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNC Falling Edge to SCLK Fall Ignore | t10 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| LDAC Pulse Width Low | t11 | 15 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNC Rising Edge to LDAC Rising Edge | t12 | 20 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| SYNC Rising Edge to LDAC Falling Edge | t13 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| LDAC Falling Edge to SYNC Rising Edge | t14 | 800 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Minimum Pulse Width Low | t15 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Pulse Activation Time | t16 | 30 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Power-Up Time (exit power-down) |  |  |  | 4.5 | µs | Exit power-down to normal mode; output unloaded | 6 |
| VDD to GND | VDD | -0.3 |  | 7 | V |  | 8 |
| VLOGIC to GND | VLOGIC | -0.3 |  | 7 | V |  | 8 |
| VOUT to GND (max = VDD + 0.3 V) | VOUT | -0.3 |  |  | V |  | 8 |
| VREF to GND (max = VDD + 0.3 V) | VREF | -0.3 |  |  | V |  | 8 |
| Digital Input Voltage to GND (max = VLOGIC + 0.3 V) |  | -0.3 |  |  | V |  | 8 |
| Operating Temperature Range |  | -40 |  | 105 | °C |  | 8 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 8 |
| Junction Temperature |  |  |  | 125 | °C |  | 8 |
| Reflow Soldering Peak Temperature, Pb Free (J-STD-020) |  |  |  | 260 | °C |  | 8 |
| Thermal Impedance, junction to ambient, 16-lead TSSOP | θJA |  | 112.6 |  | °C/W | 0 airflow, 4-layer board | 8 |

## CAD (KiCad official)

- Symbol: `AD5685RBRUZ`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad5685rbruz-etched.step` / `ad5685rbruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5685rbruz.step` / `ad5685rbruz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5686R_5685R_5684R.pdf) (29 pp, sha256 `16c7cb655e87649e`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5685rbruz-datasheet.pdf)