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AD5683RBRMZ-3-RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DAC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5683RBRMZ-3-RL7
Analog Devices · Digital To Analog Converters (DAC) · MSOP-10
AD5683RBRMZ-3-RL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input with an operating range of 2.7 V to 5.5 V, to be decoupled to GND. |
| 2 | RESET | input | Active-low hardware reset input, sensitive to a low level; when low, the device resets, ignores external pins, loads zero-scale into the input and DAC registers, and loads default values into the control register. |
| 3 | SDO | output | Serial data output used for daisy-chaining or readback of register contents; it is a push-pull output with an internal weak pull-down and is only active when DCEN is enabled or during a readback command. |
| 4 | LDAC | input | Load DAC input that transfers the input register contents to the DAC register, supports asynchronous mode, and may be tied permanently low so the DAC register updates automatically on each input-register write. |
| 5 | GND | power_in | Ground reference for all circuits on the device. |
| 6 | SCLK | input | Serial clock input; data is read into the shift register on the falling edge, at data rates up to 50 MHz. |
| 7 | SYNC | input | Active-low frame synchronization input that enables the SCLK and SDI buffers and the input shift register when low; data is read on the following 24 falling clock edges. |
| 8 | SDI | input | Serial data input to the 24-bit shift register, sampled on the falling edge of SCLK. |
| 9 | VREF | power_in | Reference voltage pin that is the output of the internal reference by default and can be used as an input for an external reference; a 10 nF decoupling capacitor to GND is recommended. |
| 10 | VOUT | output | DAC analog output voltage; the output amplifier operates rail-to-rail. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative accuracy (INL), B grade | INL | -2 | 2 | LSB | gain = 2 | 4 | |
| Relative accuracy (INL), B grade | INL | -3 | 3 | LSB | gain = 1 | 4 | |
| Differential nonlinearity (DNL) | DNL | -1 | 1 | LSB | guaranteed monotonic by design | 4 | |
| Offset error | -1.5 | 1.5 | mV | 4 | |||
| Full-scale error | -0.075 | 0.075 | % FSR | DAC register loaded with all 1s | 4 | ||
| Gain error | -0.05 | 0.05 | % FSR | 4 | |||
| Total unadjusted error (TUE) | TUE | -0.16 | 0.16 | % FSR | internal reference, gain = 1 | 4 | |
| Total unadjusted error (TUE) | TUE | -0.14 | 0.14 | % FSR | internal reference, gain = 2 | 4 | |
| Total unadjusted error (TUE) | TUE | -0.075 | 0.075 | % FSR | external reference, gain = 1 | 4 | |
| Total unadjusted error (TUE) | TUE | -0.06 | 0.06 | % FSR | external reference, gain = 2 | 4 | |
| Zero-code error drift | -1 | 1 | µV/°C | 4 | |||
| Offset error drift | -1 | 1 | µV/°C | 4 | |||
| Gain temperature coefficient | -1 | 1 | ppm/°C | 4 | |||
| Output voltage range | VOUT | 0 | V | gain = 1; upper limit printed as VREF | 4 | ||
| Capacitive load stability | CL | 2 | nF | RL = ∞ | 4 | ||
| Capacitive load stability | CL | 10 | nF | RL = 2 kΩ | 4 | ||
| Resistive load | RL | 1 | kΩ | CL = 0 µF | 4 | ||
| Short-circuit current | 20 | 30 | 50 | mA | 4 | ||
| Internal reference output voltage | VREF | 2.4975 | 2.5025 | V | ambient temperature | 5 | |
| Reference temperature coefficient | TC | 2 | 5 | ppm/°C | B grade; see Terminology | 5 | |
| Reference output current load capability | -5 | 5 | mA | VDD ≥ 3 V | 5 | ||
| Supply voltage VDD | VDD | 2.7 | 5.5 | V | gain = 1 | 5 | |
| Supply voltage VDD | VDD | 5.5 | V | gain = 2; lower limit printed as VREF + 1.5 V | 5 | ||
| Reference input range | 1 | V | upper limit printed as VDD | 5 | |||
| Logic input current | IIN | -1 | 1 | µA | per pin | 5 | |
| Logic output low voltage (SDO) | VOL | 0.4 | V | ISINK = 200 µA | 5 | ||
| Supply current, normal mode | IDD | 350 | 500 | µA | normal mode; internal reference enabled; VIH = VDD, VIL = GND | 5 | |
| Supply current, normal mode | IDD | 110 | 180 | µA | normal mode; internal reference disabled; VIH = VDD, VIL = GND | 5 | |
| Supply current, power-down mode | IDD | 2 | µA | power-down mode; DAC powered down | 5 | ||
| Output voltage settling time | 5 | 7 | µs | gain = 1 | 6 | ||
| SCLK cycle time | t1 | 20 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SCLK high time | t2 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SCLK low time | t3 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SYNC to SCLK falling edge setup time | t4 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| Data setup time | t5 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| Data hold time | t6 | 5 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SCLK falling edge to SYNC rising edge | t7 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| Minimum SYNC high time | t8 | 20 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SYNC falling edge to SCLK falling edge ignore | t9 | 10 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| SYNC rising edge to LDAC falling edge | t13 | 25 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| LDAC low pulse width | t14 | 15 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| RESET minimum low pulse width | t15 | 75 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| RESET pulse activation time | t16 | 150 | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 6 | ||
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| VOUT to GND | VOUT | -0.3 | V | upper limit printed as VDD + 0.3 V or +7 V, whichever is smaller | 8 | ||
| VREF to GND | VREF | -0.3 | V | upper limit printed as VDD + 0.3 V or +7 V, whichever is smaller | 8 | ||
| Digital input voltage to GND | -0.3 | V | upper limit printed as VDD + 0.3 V or +7 V, whichever is smaller | 8 | |||
| Operating temperature range (industrial) | TA | -40 | 105 | °C | 8 | ||
| Storage temperature range | -65 | 150 | °C | 8 | |||
| Junction temperature | TJ | 135 | °C | 8 | |||
| ESD, human body model (HBM) | 4 | kV | 8 | ||||
| ESD, field-induced charged device model (FICDM) | 1.25 | kV | 8 | ||||
| Thermal resistance, junction to ambient (10-pin MSOP) | θJA | 135 | °C/W | JEDEC 2S2P test board, still air | 8 |
CAD (KiCad official)
- Symbol:
AD5683RBRMZ-3-RL7 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad5683rbrmz-3-rl7-etched.step/ad5683rbrmz-3-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5683rbrmz-3-rl7.step/ad5683rbrmz-3-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
1f821a7da927c859, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).