# AD5676RBRUZ

**ADI(亚德诺)** · IC · TSSOP-20

AD5676RBRUZ from ADI(亚德诺), in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT1 | output | Analog output voltage from DAC 1 with rail-to-rail output amplifier operation. |
| 2 | VOUT0 | output | Analog output voltage from DAC 0 with rail-to-rail output amplifier operation. |
| 3 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V, decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 4 | VLOGIC | power_in | Digital power supply with a voltage range of 1.62 V to 5.5 V. |
| 5 | SYNC | input | Active-low frame synchronization input; data transfers in on the falling edges of the next 24 clocks when SYNC goes low. |
| 6 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 50 MHz. |
| 7 | SDI | input | Serial data input to a 24-bit input shift register, clocked on the falling edge of the serial clock. |
| 8 | GAIN | input | Span set pin: tied to GND gives 0 V to VREF output span on all eight DACs, tied to VLOGIC gives 0 V to 2 × VREF. |
| 9 | VOUT7 | output | Analog output voltage from DAC 7 with rail-to-rail output amplifier operation. |
| 10 | VOUT6 | output | Analog output voltage from DAC 6 with rail-to-rail output amplifier operation. |
| 11 | VOUT5 | output | Analog output voltage from DAC 5 with rail-to-rail output amplifier operation. |
| 12 | VOUT4 | output | Analog output voltage from DAC 4 with rail-to-rail output amplifier operation. |
| 13 | GND | power_in | Ground reference point for all circuitry on the device. |
| 14 | RSTSEL | input | Power-on reset select: tie to GND to power up all eight DACs to zero scale, or to VLOGIC to power up to midscale. |
| 15 | LDAC | input | Load DAC input operating asynchronously or synchronously; pulsing low updates DAC registers, and the pin can be tied permanently low. |
| 16 | SDO | output | Serial data output used for daisy-chaining or readback; data transfers on the rising edge of SCLK and is valid on the falling edge. |
| 17 | RESET | input | Asynchronous falling-edge-sensitive reset input; when low, LDAC pulses are ignored and DAC registers load zero or midscale per RSTSEL. |
| 18 | VREF | power_in | Reference voltage input/output; it is the reference output by default and can be disabled to use as an external reference input. |
| 19 | VOUT3 | output | Analog output voltage from DAC 3 with rail-to-rail output amplifier operation. |
| 20 | VOUT2 | output | Analog output voltage from DAC 2 with rail-to-rail output amplifier operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | ADI(亚德诺) |
| Package | TSSOP-20 |
| Category |  |
| Pins | 20 |

## CAD (KiCad official)

- Symbol: `AD5676RBRUZ`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `ad5676rbruz-etched.step` / `ad5676rbruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5676rbruz.step` / `ad5676rbruz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [ADI(亚德诺) datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5672R_5676R.pdf) (36 pp, sha256 `82203c70f66724f4`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5676rbruz-datasheet.pdf)