# AD5675BCPZ-REEL7

**Analog Devices** · Digital To Analog Converters (DACs) · LFCSP-20(4x4)

AD5675BCPZ-REEL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input; the AD5675 operates from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. |
| 2 | VLOGIC | power_in | Digital power supply; the voltage on this pin ranges from 1.62 V to 5.5 V. |
| 3 | SCL | input | Serial clock line used with SDA to clock data into or out of the 24-bit input shift register. |
| 4 | A0 | input | Address input that sets the first LSB of the 7-bit slave address. |
| 5 | A1 | input | Address input that sets the second LSB of the 7-bit slave address. |
| 6 | VOUT7 | output | Analog output voltage from DAC 7 with rail-to-rail output amplifier. |
| 7 | VOUT6 | output | Analog output voltage from DAC 6 with rail-to-rail output amplifier. |
| 8 | VOUT5 | output | Analog output voltage from DAC 5 with rail-to-rail output amplifier. |
| 9 | VOUT4 | output | Analog output voltage from DAC 4 with rail-to-rail output amplifier. |
| 10 | NIC | unconnected | No internal connection. |
| 11 | GND | power_in | Ground reference point for all circuitry on the device. |
| 12 | LDAC | input | Load DAC pin; pulsing low updates any or all DAC registers simultaneously, and it can be tied permanently low. |
| 13 | SDA | bidirectional | Bidirectional open-drain serial data line that must be pulled to the supply with an external pull-up resistor. |
| 14 | RESET | input | Asynchronous, falling-edge-sensitive reset input; when activated, the DAC registers are set to zero scale or midscale per RSTSEL, and LDAC pulses are ignored while low. |
| 15 | VREF | power_in | Reference input voltage for the DACs. |
| 16 | NIC | unconnected | No internal connection. |
| 17 | VOUT3 | output | Analog output voltage from DAC 3 with rail-to-rail output amplifier. |
| 18 | VOUT2 | output | Analog output voltage from DAC 2 with rail-to-rail output amplifier. |
| 19 | VOUT1 | output | Analog output voltage from DAC 1 with rail-to-rail output amplifier. |
| 20 | VOUT0 | output | Analog output voltage from DAC 0 with rail-to-rail output amplifier. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-20(4x4) |
| Category | ADC/DAC/Data Conversion |
| Pins | 21 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy/Integral Nonlinearity (INL) | INL | -3 | 1.8 | 3 | LSB | Gain = 1 | 3 |
| Relative Accuracy/Integral Nonlinearity (INL) | INL | -3 | 1.7 | 3 | LSB | Gain = 2 | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.7 | 1 | LSB | Gain = 1 | 3 |
| Differential Nonlinearity (DNL) | DNL | -1 | 0.5 | 1 | LSB | Gain = 2 | 3 |
| Zero Code Error |  | 0.8 |  | 1.6 | mV | Gain = 1 or gain = 2 | 3 |
| Offset Error |  | -0.75 |  | 2 | mV | Gain = 1 | 3 |
| Offset Error |  | -0.1 |  | 1.5 | mV | Gain = 2 | 3 |
| Full-Scale Error |  | -0.018 |  | 0.14 | % of full-scale range (FSR) | Gain = 1 | 3 |
| Full-Scale Error |  | -0.013 |  | 0.07 | % of FSR | Gain = 2 | 3 |
| Gain Error |  | 0.04 |  | 0.12 | % of FSR | Gain = 1 | 3 |
| Gain Error |  | -0.02 |  | 0.06 | % of FSR | Gain = 2 | 3 |
| Total Unadjusted Error (TUE) | TUE | -0.18 | 0.03 | 0.18 | % of FSR | Gain = 1 | 3 |
| Total Unadjusted Error (TUE) | TUE | -0.14 | 0.006 | 0.14 | % of FSR | Gain = 2 | 3 |
| Offset Error Drift |  | -1 |  | 1 | µV/°C |  | 3 |
| DC Power Supply Rejection Ratio (PSRR) | PSRR |  |  | 0.25 | mV/V | DAC code = midscale, VDD = 5 V ± 10% | 3 |
| Output Voltage Range | VOUT | 0 |  |  | V | Gain = 1; upper limit VREF | 3 |
| Capacitive Load Stability | CL |  |  | 2 | nF | RL = ∞ | 3 |
| Capacitive Load Stability | CL |  |  | 10 | nF | RL = 1 kΩ | 3 |
| Resistive Load | RL | 1 |  |  | kΩ |  | 3 |
| Reference Input Range | VREF | 1 |  |  | V | Gain = 1; upper limit VDD | 3 |
| Input Current | IIN | -1 |  | 1 | µA | Per pin | 4 |
| Output Voltage Low | VOL |  |  | 0.4 | V | ISINK = 200 μA | 4 |
| VLOGIC Supply Voltage | VLOGIC | 1.62 |  | 5.5 | V |  | 4 |
| VLOGIC Supply Current (ILOGIC) | ILOGIC |  |  | 3 | µA | Power-on, −40°C to +105°C | 4 |
| VDD Supply Voltage | VDD | 2.7 |  | 5.5 | V | Gain = 1 | 4 |
| VDD Supply Voltage | VDD |  |  | 5.5 | V | Gain = 2; minimum VREF + 1.5 | 4 |
| VDD Supply Current, Normal Mode | IDD | 1.1 |  | 1.26 | mA | −40°C to +85°C | 4 |
| VDD Supply Current, Normal Mode | IDD | 1.1 |  | 1.3 | mA | −40°C to +125°C | 4 |
| All Power-Down Modes Supply Current | IDD | 1 |  | 1.7 | µA | Tristate to 1 kΩ, −40°C to +85°C | 4 |
| All Power-Down Modes Supply Current | IDD | 1 |  | 2.5 | µA | Tristate to 1 kΩ, −40°C to +105°C | 4 |
| All Power-Down Modes Supply Current | IDD | 1 |  | 5.5 | µA | Tristate to 1 kΩ, −40°C to +125°C | 4 |
| VDD to GND | VDD | -0.3 |  | 7 | V |  | 7 |
| VLOGIC to GND | VLOGIC | -0.3 |  | 7 | V |  | 7 |
| Operating Temperature Range | TA | -40 |  | 125 | °C |  | 7 |
| Storage Temperature Range | TSTG | -65 |  | 150 | °C |  | 7 |
| Junction Temperature | TJ |  |  | 125 | °C |  | 7 |
| Thermal Resistance, junction-to-ambient, 20-Lead LFCSP (CP-20-8) | θJA |  | 82 |  | °C/W |  | 7 |
| Thermal Resistance, junction-to-board, 20-Lead LFCSP (CP-20-8) | θJB |  | 16.67 |  | °C/W |  | 7 |
| Thermal Resistance, junction-to-case, 20-Lead LFCSP (CP-20-8) | θJC |  | 32.5 |  | °C/W |  | 7 |
| SCL Cycle Time | t1 | 2.5 |  |  | µs |  | 5 |
| tHIGH, SCL High Time | t2 | 0.6 |  |  | µs |  | 5 |
| tSU,DAT, Data Setup Time | t5 | 100 |  |  | ns |  | 5 |
| tHD,DAT, Data Hold Time | t6 | 0 |  | 0.9 | µs |  | 5 |
| tR, Rise Time of SCL and SDA when receiving | t10 | 0 |  | 300 | ns |  | 5 |
| LDAC Pulse Width | t12 | 20 |  |  | ns |  | 5 |
| RESET Minimum Pulse Width Low | t14 | 8 |  |  | ns | 1.62 V ≤ VLOGIC ≤ 2.7 V | 5 |
| RESET Minimum Pulse Width Low | t14 | 10 |  |  | ns | 2.7 V ≤ VLOGIC ≤ 5.5 V | 5 |
| Output Current Drive | IOUT |  | 15 |  | mA |  | 3 |
| Short-Circuit Current | ISC |  | 40 |  | mA |  | 3 |
| Load Impedance at Rails |  |  | 25 |  | Ω |  | 3 |
| Power-Up Time |  |  | 2.5 |  | µs | Exiting power-down mode, VDD = 5 V | 3 |
| Reference Input Current | IREF |  | 398 |  | µA | VREF = VDD = VLOGIC = 5.5 V, gain = 1 | 3 |
| Reference Input Current | IREF |  | 789 |  | µA | VREF = VDD = VLOGIC = 5.5 V, gain = 2 | 3 |

## CAD (KiCad official)

- Symbol: `AD5675BCPZ-REEL7`
- Footprint: `Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm`
- 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
- 3D model files: `ad5675bcpz-reel7-etched.step` / `ad5675bcpz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5675bcpz-reel7.step` / `ad5675bcpz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5675.pdf) (27 pp, sha256 `b599435e313f9464`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5675bcpz-reel7-datasheet.pdf)