AD5671RBRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VOUT1	output	Analog output voltage from DAC 1, with an output amplifier that has rail-to-rail operation.
2	VOUT0	output	Analog output voltage from DAC 0, with an output amplifier that has rail-to-rail operation.
3	VDD	power_in	Power supply input that operates from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4	VLOGIC	power_in	Digital power supply whose voltage ranges from 1.62 V to 5.5 V.
5	SCL	input	Serial clock line that, in conjunction with SDA, clocks data into or out of the 24-bit input shift register.
6	A0	input	Address input that sets the first LSB of the 7-bit I2C slave address.
7	A1	input	Address input that sets the second LSB of the 7-bit I2C slave address.
8	GAIN	input	Span set pin where tying it to GND gives all eight DAC outputs a 0 V to VREF span and tying it to VLOGIC gives a 0 V to 2 × VREF span.
9	VOUT7	output	Analog output voltage from DAC 7, with an output amplifier that has rail-to-rail operation.
10	VOUT6	output	Analog output voltage from DAC 6, with an output amplifier that has rail-to-rail operation.
11	VOUT5	output	Analog output voltage from DAC 5, with an output amplifier that has rail-to-rail operation.
12	VOUT4	output	Analog output voltage from DAC 4, with an output amplifier that has rail-to-rail operation.
13	GND	power_in	Ground reference point for all circuitry on the device.
14	RSTSEL	input	Power-on reset pin where tying it to GND powers up all eight DACs to zero scale and tying it to VLOGIC powers them up to midscale.
15	LDAC	input	Load DAC pin that, when pulsed low, updates any or all DAC registers with new input-register data simultaneously, and it can be tied permanently low.
16	SDA	bidirectional	Bidirectional open-drain serial data line that must be pulled to the supply with an external pull-up resistor.
17	RESET	input	Asynchronous, falling-edge-sensitive reset input where, while low, all LDAC pulses are ignored and the DAC registers are loaded with zero scale or midscale per RSTSEL.
18	VREFOUT	output	Reference output voltage pin, which is the reference output by default when the internal reference is used.
19	VOUT3	output	Analog output voltage from DAC 3, with an output amplifier that has rail-to-rail operation.
20	VOUT2	output	Analog output voltage from DAC 2, with an output amplifier that has rail-to-rail operation.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20
Category	ADC/DAC/Data Conversion
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (INL), Gain = 1		-1	0.12	1	LSB	Gain = 1	4
Relative Accuracy (INL), Gain = 2		-1	0.12	1	LSB	Gain = 2	4
Differential Nonlinearity (DNL), Gain = 1		-0.1	0.01	0.1	LSB	Gain = 1	4
Differential Nonlinearity (DNL), Gain = 2		-0.1	0.01	0.1	LSB	Gain = 2	4
Zero Code Error			0.8	1.6	mV	Gain = 1 or gain = 2	4
Offset Error, Gain = 1		-2	-0.75	2	mV	Gain = 1	4
Offset Error, Gain = 2		-1.5	-0.1	1.5	mV	Gain = 2	4
Full-Scale Error, Gain = 1		-0.14	-0.018	0.14	% of FSR	Gain = 1	4
Full-Scale Error, Gain = 2		-0.07	-0.013	0.07	% of FSR	Gain = 2	4
Gain Error, Gain = 1		-0.12	0.04	0.12	% of FSR	Gain = 1	4
Gain Error, Gain = 2		-0.06	-0.02	0.06	% of FSR	Gain = 2	4
Total Unadjusted Error (TUE), Gain = 1	TUE	-0.18	0.03	0.18	% of FSR	Gain = 1	4
Total Unadjusted Error (TUE), Gain = 2	TUE	-0.14	0.006	0.14	% of FSR	Gain = 2	4
Output Voltage Range, Gain = 1		0		2.5	V	Gain = 1	4
Output Voltage Range, Gain = 2		0		5	V	Gain = 2	4
Capacitive Load Stability				2	nF	RL = ∞	4
Capacitive Load Stability				10	nF	RL = 1 kΩ	4
Output Current Load Capability		-20		20	mA	VDD ≥ 3 V	5
Reference Output Voltage		2.4975		2.5025	V		4
Reference Temperature Coefficient, 20-Lead TSSOP			2	5	ppm/°C	Box method, −40°C to +125°C	4
Long-Term Stability/Drift			12		ppm	After 1000 hours at 125°C	5
Thermal Hysteresis, first cycle			125		ppm	First cycle	5
Thermal Hysteresis, additional cycles			25		ppm	Additional cycles	5
Input Current		-1		1	µA	Per pin	5
Output Voltage Low (SDA)	VOL			0.4	V	IOL = 200 µA	5
Pin Capacitance (logic inputs)			3		pF		5
Floating State Output Capacitance (SDA)			4		pF		5
VLOGIC supply voltage	VLOGIC	1.62		5.5	V		4
VDD supply voltage, Gain = 1	VDD	2.7		5.5	V	Gain = 1	5
VDD supply voltage, Gain = 2	VDD			5.5	V	Gain = 2 (minimum is VREF + 1.5 V)	5
VDD Supply Current, normal mode, internal reference off	IDD		1.1	1.26	mA	Internal reference off, −40°C to +85°C	5
VDD Supply Current, normal mode, internal reference on	IDD		1.8	2	mA	Internal reference on, −40°C to +85°C	5
VDD Supply Current, normal mode, internal reference off	IDD		1.1	1.3	mA	Internal reference off	5
VDD Supply Current, normal mode, internal reference on	IDD		1.8	2.1	mA	Internal reference on	5
All Power-Down Modes, tristate to 1 kΩ	IDD		1	1.7	µA	Tristate to 1 kΩ, −40°C to +85°C	5
All Power-Down Modes, power-down to 1 kΩ	IDD		1	1.7	µA	Power-down to 1 kΩ, −40°C to +85°C	5
All Power-Down Modes, tristate	IDD		1	2.5	µA	Tristate, −40°C to +105°C	5
All Power-Down Modes, power-down to 1 kΩ	IDD		1	2.5	µA	Power-down to 1 kΩ, −40°C to +105°C	5
All Power-Down Modes, tristate to 1 kΩ	IDD		1	5.5	µA	Tristate to 1 kΩ, −40°C to +125°C	5
All Power-Down Modes, power-down to 1 kΩ	IDD		1	5.5	µA	Power-down to 1 kΩ, −40°C to +125°C	5
Output Voltage Settling Time, ¼ to ¾ scale			5	8	µs	Settling to ±2 LSB	8
Slew Rate			0.8		V/µs		8
Digital-to-Analog Glitch Impulse			1.4		nV-sec	1 LSB change around major carry, internal reference, gain = 1	8
Digital Crosstalk			0.1		nV-sec		8
Analog Crosstalk			-0.25		nV-sec		8
Analog Crosstalk			-1.3		nV-sec	Internal reference, gain = 2	8
Output Noise Spectral Density			300		nV/√Hz	DAC code = midscale, 10 kHz; gain = 2	8
Output Noise			6		µV p-p	0.1 Hz to 10 Hz, gain = 1	8
SCL cycle time	t1	2.5			µs		9
tHIGH, SCL high time	t2	0.6			µs		9
tLOW, SCL low time	t3	1.3			µs		9
tHD,STA, start/repeated start hold time	t4	0.6			µs		9
tSU,DAT, data setup time	t5	100			ns		9
tHD,DAT, data hold time	t6	0		0.9	µs	Master must provide ≥300 ns hold, see footnote 2	9
tSU,STA, repeated start setup time	t7	0.6			µs		9
tSU,STO, stop condition setup time	t8	0.6			µs		9
tBUF, bus free time	t9	1.3			µs		9
tR, rise time of SCL and SDA when receiving	t10	0		300	ns		9
LDAC pulse width	t12	20			ns		9
SCL rising edge to LDAC rising edge	t13	400			ns		9
RESET minimum pulse width low	t14	8			ns	1.62 V ≤ VLOGIC ≤ 2.7 V	9
RESET minimum pulse width low	t14	10			ns	2.7 V ≤ VLOGIC ≤ 5.5 V	9
RESET activation time	t15			90	ns	1.62 V ≤ VLOGIC ≤ 2.7 V; 2.7 V ≤ VLOGIC ≤ 5.5 V	9
Pulse width of suppressed spike	tSP	0		50	ns		9
VDD to GND	VDD	-0.3		7	V		10
VLOGIC to GND	VLOGIC	-0.3		7	V		10
VOUTx to GND	VOUTx	-0.3			V	Max is VDD + 0.3 V	10
VREFOUT to GND	VREFOUT	-0.3			V	Max is VDD + 0.3 V	10
Digital Input Voltage to GND		-0.3			V	Max is VLOGIC + 0.3 V	10
Operating Temperature Range		-40		125	°C		10
Storage Temperature Range		-65		150	°C		10
Junction Temperature				125	°C		10
Reflow Soldering Peak Temperature, Pb Free				260	°C	J-STD-020	10
Thermal Resistance, junction-to-ambient	θJA		98.65		°C/W	20-Lead TSSOP (RU-20), JEDEC 2S2P board	10
Thermal Resistance, junction-to-board	θJB		44.39		°C/W	20-Lead TSSOP (RU-20), JEDEC 2S2P board	10
Thermal Resistance, junction-to-case	θJC		17.58		°C/W	20-Lead TSSOP (RU-20), JEDEC 2S2P board	10

CAD (KiCad official)

Symbol: AD5671RBRUZ
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ad5671rbruz-etched.step / ad5671rbruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5671rbruz.step / ad5671rbruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (33 pp, sha256 1d50698f29448fac, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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AD5671RBRUZ

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