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AD5668ARUZ-3

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Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5668aruz-3factory-2.0.0extractor-text

Verified AD5668ARUZ-3

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5668ARUZ-3 · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 30-page datasheet
  • ✓distributor: lcsc C578263, digikey 505-AD5668ARUZ-3-ND, mouser 584-AD5668ARUZ-3
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-7f5fd8ib/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5668aruz-3.kicad_sym✓ ad5668aruz-3.kicad_mod✓ ad5668aruz-3.step
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Ray Publish 0.1.0 461eb39 17h ago

AD5668ARUZ-3

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD5668ARUZ-3 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, and it can alternatively be tied permanently low.
2 SYNC input Active-low frame synchronization input: data is clocked in on the falling edges of the next 32 clocks, and a rising edge of SYNC before the 32nd falling edge aborts the write.
3 VDD power_in Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VOUTA output Analog output voltage from DAC A, driven by an output amplifier with rail-to-rail operation.
5 VOUTC output Analog output voltage from DAC C, driven by an output amplifier with rail-to-rail operation.
6 VOUTE output Analog output voltage from DAC E, driven by an output amplifier with rail-to-rail operation.
7 VOUTG output Analog output voltage from DAC G, driven by an output amplifier with rail-to-rail operation.
8 VREFIN/VREFOUT bidirectional Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input.
9 CLR input Asynchronous falling-edge-sensitive clear input that loads the CLR code (zero, midscale or full scale) into the DAC registers, defaulting to 0 V, and all LDAC pulses are ignored while CLR is low.
10 VOUTH output Analog output voltage from DAC H, driven by an output amplifier with rail-to-rail operation.
11 VOUTF output Analog output voltage from DAC F, driven by an output amplifier with rail-to-rail operation.
12 VOUTD output Analog output voltage from DAC D, driven by an output amplifier with rail-to-rail operation.
13 VOUTB output Analog output voltage from DAC B, driven by an output amplifier with rail-to-rail operation.
14 GND power_in Ground reference point for all circuitry on the part.
15 DIN input Serial data input to the 32-bit shift register, with data clocked in on the falling edge of the serial clock.
16 SCLK input Serial clock input with data clocked into the input shift register on falling edges, supporting rates of up to 50 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (AD5668) INL -32 8 32 LSB See Figure 7 4
Differential Nonlinearity (AD5668) DNL -1 1 LSB Guaranteed monotonic by design (see Figure 10) 4
Zero-Code Error 6 19 mV All 0s loaded to DAC register (see Figure 26) 4
Zero-Code Error Drift -2 2 μV/°C 4
Full-Scale Error -0.2 -1 % FSR All 1s loaded to DAC register (see Figure 27) 4
Gain Error -1 1 % FSR 4
Gain Temperature Coefficient -2.5 2.5 ppm of FSR/°C 4
Offset Error 6 19 mV 4
DC Power Supply Rejection Ratio PSRR -80 dB VDD ± 10% 4
DC Crosstalk (External Reference) 10 μV Due to full-scale output change, RL = 2 kΩ to GND or VDD 4
DC Crosstalk (External Reference) load current 5 μV/mA Due to load current change 4
DC Crosstalk (External Reference) power down 10 μV Due to powering down (per channel) 4
DC Crosstalk (Internal Reference) 25 μV Due to full-scale output change, RL = 2 kΩ to GND or VDD 4
DC Crosstalk (Internal Reference) load current 10 μV/mA Due to load current change 4
Capacitive Load Stability 2 nF RL = ∞ 4
Capacitive Load Stability 10 nF RL = 2 kΩ 4
DC Output Impedance 0.5 Ω 4
Short-Circuit Current 30 mA VDD = 5 V 4
Power-Up Time 4 μs Coming out of power-down mode, VDD = 5 V 4
Reference Current 40 55 μA VREF = VDD = 5.5 V (per DAC channel) 4
Reference Input Impedance 14.6 kΩ 4
Output Voltage (AD5668-3 reference) VREFOUT 2.495 2.505 V At ambient 4
Reference TC (TSSOP) 5 10 ppm/°C TSSOP 4
Reference Output Impedance 7.5 kΩ 4
Input Current -3 3 µA All digital inputs 5
Input Low Voltage VINL 0.8 V VDD = 5 V 5
Input High Voltage VINH 2 V VDD = 5 V 5
Pin Capacitance 3 pF 5
Supply Voltage VDD 4.5 5.5 V All digital inputs at 0 or VDD, DAC active, excludes load current 5
IDD (Normal Mode), internal reference off IDD 1 1.5 mA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference off 5
IDD (Normal Mode), internal reference on IDD 1.8 2.25 mA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference on 5
IDD (All Power-Down Modes) IDD 0.4 1 µA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 5
SCLK cycle time t1 20 ns VDD = 2.7 V to 5.5 V 8
SCLK high time t2 8 ns VDD = 2.7 V to 5.5 V 8
SCLK low time t3 8 ns VDD = 2.7 V to 5.5 V 8
SYNC to SCLK falling edge set-up time t4 13 ns VDD = 2.7 V to 5.5 V 8
Data set-up time t5 4 ns VDD = 2.7 V to 5.5 V 8
Data hold time t6 4 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 8
Minimum SYNC high time t8 15 ns VDD = 2.7 V to 5.5 V 8
SYNC rising edge to SCLK fall ignore t9 13 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC fall ignore t10 0 ns VDD = 2.7 V to 5.5 V 8
LDAC pulse width low t11 10 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC rising edge t12 15 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC falling edge t14 0 ns VDD = 2.7 V to 5.5 V 8
CLR pulse width low t13 5 ns VDD = 2.7 V to 5.5 V 8
CLR pulse activation time t15 300 ns VDD = 2.7 V to 5.5 V 8
Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB (16-bit resolution) 7
Slew Rate 1.2 V/µs 7
Multiplying Bandwidth 320 kHz VREF = 2 V ± 0.2 V p-p 7
Total Harmonic Distortion -80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz 7
Output Noise Spectral Density (1 kHz) 120 nV/√Hz DAC code = 0x8400 (16-bit resolution), 1 kHz 7
Output Noise Spectral Density (10 kHz) 100 nV/√Hz DAC code = 0x8400 (16-bit resolution), 10 kHz 7
Output Noise 0.1 Hz to 10 Hz 12 µV p-p DAC code = 0x0000 7
VDD to GND VDD -0.3 7 V 9
Operating Temperature Range (Industrial) -40 105 °C Industrial 9
Storage Temperature Range -65 150 °C 9
Junction Temperature TJ 150 °C TJ MAX 9
Reflow Soldering Peak Temperature 260 °C Pb Free 9
Digital Input Voltage to GND -0.3 V Maximum printed as VDD + 0.3 V 9
VOUT to GND VOUT -0.3 V Maximum printed as VDD + 0.3 V 9
VREFIN/VREFOUT to GND VREFIN/VREFOUT -0.3 V Maximum printed as VDD + 0.3 V 9
Thermal Resistance, junction to ambient (RU-16) θJA 113.5 °C/W RU-16 package 9
Thermal Resistance, junction to case (RU-16) θJC 35 °C/W RU-16 package 9

CAD (KiCad official)

  • Symbol: AD5668ARUZ-3
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad5668aruz-3-etched.step / ad5668aruz-3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5668aruz-3.step / ad5668aruz-3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (30 pp, sha256 aa0519e5e63a0198, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF