AD5666BRUZ-2REEL7

{
  "slug": "ad5666bruz-2reel7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "data acquisition",
    "ad5666bruz-2reel7",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "AD5666BRUZ-2REEL7",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-14",
    "pin_count": 14,
    "category": "Data Acquisition",
    "subcategory": "Digital To Analog Converters (DAC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588884893446758400",
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    "distributor_links": {
      "lcsc": "C514223"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T23:47:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
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      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "LDAC",
        "type": "input",
        "description": "Pulsing this pin low updates any or all DAC registers whose input registers hold new data, so all DAC outputs update simultaneously; it can alternatively be tied permanently low."
      },
      {
        "number": "2",
        "name": "SYNC",
        "type": "input",
        "description": "Active-low frame sync input that powers on SCLK and DIN buffers; 32 data bits are clocked in on the falling edges of the next 32 clocks, and a SYNC rising edge before the 32nd falling edge aborts the write."
      },
      {
        "number": "3",
        "name": "VDD",
        "type": "power_in",
        "description": "Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND."
      },
      {
        "number": "4",
        "name": "VOUTA",
        "type": "output",
        "description": "Analog output voltage from DAC A, driven by an output amplifier with rail-to-rail operation."
      },
      {
        "number": "5",
        "name": "VOUTC",
        "type": "output",
        "description": "Analog output voltage from DAC C, driven by an output amplifier with rail-to-rail operation."
      },
      {
        "number": "6",
        "name": "POR",
        "type": "input",
        "description": "Power-on reset pin: tying it to GND powers the part up with outputs at 0 V, and tying it to VDD powers up to midscale."
      },
      {
        "number": "7",
        "name": "VREFIN/VREFOUT",
        "type": "bidirectional",
        "description": "Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input."
      },
      {
        "number": "8",
        "name": "SDO",
        "type": "output",
        "description": "Serial data output for daisy-chaining devices or reading back the shift register; data is transferred on the rising SCLK edge and is valid on the falling edge."
      },
      {
        "number": "9",
        "name": "CLR",
        "type": "input",
        "description": "Falling-edge-sensitive asynchronous clear input that, when low, causes LDAC pulses to be ignored and clears the DACs to the programmed CLR code (zero, midscale, or full scale), defaulting to 0 V."
      },
      {
        "number": "10",
        "name": "VOUTD",
        "type": "output",
        "description": "Analog output voltage from DAC D, driven by an output amplifier with rail-to-rail operation."
      },
      {
        "number": "11",
        "name": "VOUTB",
        "type": "output",
        "description": "Analog output voltage from DAC B, driven by an output amplifier with rail-to-rail operation."
      },
      {
        "number": "12",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for all circuitry on the part."
      },
      {
        "number": "13",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to a 32-bit shift register, clocked in on the falling edge of SCLK."
      },
      {
        "number": "14",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input that clocks data into the input shift register on its falling edge, at rates of up to 50 MHz."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package mapping confirmed: the ordering guide (page 27) lists AD5666BRUZ-2REEL7 as 14-Lead TSSOP, pa; Pin types are KiCad-class judgments, not stated in the datasheet. The DAC outputs (VOUTA-VOUTD) are "
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        "cost_usd": 0.0458,
        "at": "2026-10-18T23:47:41"
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        "pages": 28,
        "sha256": "42ddb93a8b652c8c",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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}