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AD5666BRUZ-2REEL7

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Analog Devices Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD5666BRUZ-2REEL7

Analog Devices · Digital To Analog Converters (DAC) · TSSOP-14

AD5666BRUZ-2REEL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Pulsing this pin low updates any or all DAC registers whose input registers hold new data, so all DAC outputs update simultaneously; it can alternatively be tied permanently low.
2 SYNC input Active-low frame sync input that powers on SCLK and DIN buffers; 32 data bits are clocked in on the falling edges of the next 32 clocks, and a SYNC rising edge before the 32nd falling edge aborts the write.
3 VDD power_in Power supply input operating from 2.7 V to 5.5 V, to be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VOUTA output Analog output voltage from DAC A, driven by an output amplifier with rail-to-rail operation.
5 VOUTC output Analog output voltage from DAC C, driven by an output amplifier with rail-to-rail operation.
6 POR input Power-on reset pin: tying it to GND powers the part up with outputs at 0 V, and tying it to VDD powers up to midscale.
7 VREFIN/VREFOUT bidirectional Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, defaulting to reference input.
8 SDO output Serial data output for daisy-chaining devices or reading back the shift register; data is transferred on the rising SCLK edge and is valid on the falling edge.
9 CLR input Falling-edge-sensitive asynchronous clear input that, when low, causes LDAC pulses to be ignored and clears the DACs to the programmed CLR code (zero, midscale, or full scale), defaulting to 0 V.
10 VOUTD output Analog output voltage from DAC D, driven by an output amplifier with rail-to-rail operation.
11 VOUTB output Analog output voltage from DAC B, driven by an output amplifier with rail-to-rail operation.
12 GND power_in Ground reference point for all circuitry on the part.
13 DIN input Serial data input to a 32-bit shift register, clocked in on the falling edge of SCLK.
14 SCLK input Serial clock input that clocks data into the input shift register on its falling edge, at rates of up to 50 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category Data Acquisition
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -16 16 LSB See Figure 6 3
Differential Nonlinearity -1 1 LSB Guaranteed monotonic by design (see Figure 7) 3
Zero-Code Error 1 9 mV All 0s loaded to DAC register (see Figure 13) 3
Zero-Code Error Drift -2 2 μV/°C 3
Full-Scale Error -0.2 -1 % FSR All 1s loaded to DAC register (see Figure 12) 3
Gain Error -1 1 % FSR 3
Gain Temperature Coefficient -2.5 2.5 ppm Of FSR/°C 3
Offset Error -9 1 9 mV 3
DC Power Supply Rejection Ratio -80 dB VDD ± 10% 3
Output Voltage Range 0 V Maximum is VDD (printed as VDD); left null 3
Short-Circuit Current 30 mA VDD = 5 V 3
Reference Current 20 55 μA VREF = VDD = 5.5 V 3
Reference Output Voltage 2.495 2.505 V At ambient 3
Reference TC -10 5 10 ppm/°C 3
Input Current -3 3 μA All digital inputs 3
Input Low Voltage VINL 0.8 V VDD = 5 V 3
Input High Voltage VINH 2 V VDD = 5 V 3
Output Low Voltage (SDO) VOL 0.4 V ISINK = 2 mA 4
High Impedance Leakage Current (SDO) -0.25 0.25 μA 4
Supply Voltage VDD VDD 4.5 5.5 V All digital inputs at 0 or VDD, DAC active, excludes load current 4
IDD Normal Mode, Internal Reference Off IDD 0.7 0.9 mA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference off 4
IDD Normal Mode, Internal Reference On IDD 1.3 1.6 mA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; internal reference on 4
IDD All Power-Down Modes IDD 0.4 1 μA VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 4
Supply Voltage VDD (2.7 V to 3.6 V range) VDD 2.7 3.6 V All digital inputs at 0 or VDD, DAC active, excludes load current 6
IDD Normal Mode, Internal Reference Off (2.7 V to 3.6 V) IDD 0.65 0.85 mA VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; internal reference off 6
IDD Normal Mode, Internal Reference On (2.7 V to 3.6 V) IDD 1.3 1.5 mA VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; internal reference on 6
IDD All Power-Down Modes (2.7 V to 3.6 V) IDD 0.2 1 μA VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND 6
Output Voltage Settling Time 6 10 μs ¼ to ¾ scale settling to ±2 LSB 7
Slew Rate 1.5 V/μs 7
Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 29) 7
Total Harmonic Distortion -80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz 7
SCLK cycle time t1 20 ns VDD = 2.7 V to 5.5 V; maximum SCLK frequency 50 MHz 8
SCLK high time t2 8 ns VDD = 2.7 V to 5.5 V 8
SCLK low time t3 8 ns VDD = 2.7 V to 5.5 V 8
SYNC to SCLK falling edge set-up time t4 13 ns VDD = 2.7 V to 5.5 V 8
Data set-up time t5 4 ns VDD = 2.7 V to 5.5 V 8
Data hold time t6 4 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 8
Minimum SYNC high time t8 15 ns VDD = 2.7 V to 5.5 V 8
SYNC rising edge to SCLK fall ignore t9 13 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC fall ignore t10 0 ns VDD = 2.7 V to 5.5 V 8
LDAC pulse width low t11 10 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC rising edge t12 15 ns VDD = 2.7 V to 5.5 V 8
CLR pulse width low t13 5 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC falling edge t14 0 ns VDD = 2.7 V to 5.5 V 8
CLR pulse activation time t15 300 ns VDD = 2.7 V to 5.5 V 8
SCLK rising edge to SDO valid t16 22 ns VDD = 2.7 V to 5.5 V; daisy-chain mode only; measured with load circuit of Figure 16 8
SCLK falling edge to SYNC rising edge t17 5 ns VDD = 2.7 V to 5.5 V; daisy-chain mode only 8
SYNC rising edge to SCLK rising edge t18 8 ns VDD = 2.7 V to 5.5 V; daisy-chain mode only 8
SYNC rising edge to LDAC falling edge t19 0 ns VDD = 2.7 V to 5.5 V; daisy-chain mode only 8
VDD to GND VDD -0.3 7 V Referenced to GND 10
Digital Input Voltage to GND -0.3 V Printed maximum is VDD + 0.3 V; left null 10
VOUT to GND VOUT -0.3 V Printed maximum is VDD + 0.3 V; left null 10
VREFIN/VREFOUT to GND -0.3 V Printed maximum is VDD + 0.3 V; left null 10
Operating Temperature Range (Industrial) TA -40 105 °C Industrial 10
Storage Temperature Range -65 150 °C 10
Junction Temperature (TJ MAX) TJ MAX 150 °C 10
Reflow Soldering Peak Temperature 260 °C Pb Free 10
θJA Thermal Impedance (TSSOP) θJA 150.4 °C/W TSSOP package 10

CAD (KiCad official)

  • Symbol: AD5666BRUZ-2REEL7
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ad5666bruz-2reel7-etched.step / ad5666bruz-2reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5666bruz-2reel7.step / ad5666bruz-2reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 42ddb93a8b652c8c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF