component

AD5666ARUZ-2REEL7

Public Made by Adom

by adom

Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5666aruz-2reel7factory-2.0.0extractor-text

Verified AD5666ARUZ-2REEL7

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5666ARUZ-2REEL7 · TSSOP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 28-page datasheet
  • ✓distributor: lcsc C649997, digikey 505-AD5666ARUZ-2REEL7TR-ND, mouser 584-AD5666ARUZ-2R7
  • ✓family: TSSOP-14_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-tkaryxc0/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.27)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5666aruz-2reel7.kicad_sym✓ ad5666aruz-2reel7.kicad_mod✓ ad5666aruz-2reel7.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers ad5666aruz-2reel7: viewers · Ray 2d ago
ad5666aruz-2reel7-etched.glb Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7-etched.step ad5666aruz-2reel7: factory component page (tier=mfr) · Ray 2d ago
ad5666aruz-2reel7-hero.glb ad5666aruz-2reel7: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ad5666aruz-2reel7-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7.glb Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7.kicad_mod Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7.kicad_sym Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7.lbr Publish 0.1.0 · Ray 2d ago
ad5666aruz-2reel7.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 2d ago

AD5666ARUZ-2REEL7

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-14

AD5666ARUZ-2REEL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Pulsing this pin low updates any or all DAC registers if the input registers have new data, so all DAC outputs update simultaneously; it can alternatively be tied permanently low.
2 SYNC input Active-low frame synchronization input; going low powers on the SCLK and DIN buffers and enables the input shift register, with data transferred on the falling edges of the next 32 clocks, and a rising edge before the 32nd falling edge interrupts and ignores the write.
3 VDD power_in Power supply input for 2.7 V to 5.5 V operation, decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
4 VOUTA output Analog output voltage from DAC A with rail-to-rail output amplifier.
5 VOUTC output Analog output voltage from DAC C with rail-to-rail output amplifier.
6 POR input Power-on reset pin; tying it to GND powers up the part to 0 V and tying it to VDD powers up the part to midscale.
7 VREFIN/VREFOUT bidirectional Common reference input/output pin that is the reference output when using the internal reference and the reference input when using an external reference, defaulting to reference input.
8 SDO output Serial data output for daisy-chaining devices or reading back the shift register, transferred on the rising edge of SCLK and valid on the falling edge of the clock.
9 CLR input Asynchronous falling-edge-sensitive clear input; when low all LDAC pulses are ignored, and when activated the input and DAC registers load the CLR code register value (zero, midscale or full scale, default 0 V).
10 VOUTD output Analog output voltage from DAC D with rail-to-rail output amplifier.
11 VOUTB output Analog output voltage from DAC B with rail-to-rail output amplifier.
12 GND power_in Ground reference point for all circuitry on the part.
13 DIN input Serial data input to the 32-bit shift register, clocked in on the falling edge of the serial clock input.
14 SCLK input Serial clock input; data is clocked into the input shift register on the falling edge, at rates of up to 50 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -32 32 LSB See Figure 6 3
Differential Nonlinearity -1 1 LSB Guaranteed monotonic by design 3
Zero-Code Error 1 9 mV All 0s loaded to DAC register 3
Full-Scale Error -0.2 -1 % FSR All 1s loaded to DAC register 3
Gain Error -1 1 % FSR 3
Offset Error 1 9 mV 3
Output Voltage Range (min) 0 V 3
Reference Current 20 55 μA VREF = VDD = 5.5 V 3
Reference Output Voltage 2.495 2.505 V At ambient 3
Reference TC 5 10 ppm/°C 3
Logic Input Current -3 3 μA All digital inputs 3
Input Low Voltage VINL 0.8 V VDD = 5 V 3
Input High Voltage VINH 2 V VDD = 5 V 3
Output Low Voltage VOL 0.4 V ISINK = 2 mA 4
Supply Voltage VDD 4.5 5.5 V All digital inputs at 0 or VDD, DAC active, excludes load current 4
IDD Normal Mode, internal reference off IDD 0.7 0.9 mA VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND 4
IDD Normal Mode, internal reference on IDD 1.3 1.6 mA VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND 4
IDD All Power-Down Modes IDD 0.4 1 μA VDD = 4.5 V to 5.5 V, VIH = VDD and VIL = GND 4
Output Voltage Settling Time 6 10 μs ¼ to ¾ scale settling to ±2 LSB 7
SCLK cycle time t1 20 ns VDD = 2.7 V to 5.5 V 8
SCLK high time t2 8 ns VDD = 2.7 V to 5.5 V 8
SCLK low time t3 8 ns VDD = 2.7 V to 5.5 V 8
SYNC to SCLK falling edge set-up time t4 13 ns VDD = 2.7 V to 5.5 V 8
Data set-up time t5 4 ns VDD = 2.7 V to 5.5 V 8
Data hold time t6 4 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 8
Minimum SYNC high time t8 15 ns VDD = 2.7 V to 5.5 V 8
SYNC rising edge to SCLK fall ignore t9 13 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to SYNC fall ignore t10 0 ns VDD = 2.7 V to 5.5 V 8
LDAC pulse width low t11 10 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC rising edge t12 15 ns VDD = 2.7 V to 5.5 V 8
CLR pulse width low t13 5 ns VDD = 2.7 V to 5.5 V 8
SCLK falling edge to LDAC falling edge t14 0 ns VDD = 2.7 V to 5.5 V 8
CLR pulse activation time t15 300 ns VDD = 2.7 V to 5.5 V 8
SCLK rising edge to SDO valid t16 22 ns Daisy-chain mode only; load circuit of Figure 16 8
SCLK falling edge to SYNC rising edge (daisy-chain) t17 5 ns Daisy-chain mode only 8
SYNC rising edge to SCLK rising edge t18 8 ns Daisy-chain mode only 8
SYNC rising edge to LDAC falling edge t19 0 ns Daisy-chain mode only 8
VDD to GND -0.3 7 V TA = 25°C 10
Digital Input Voltage to GND -0.3 V Max is VDD + 0.3 V; TA = 25°C 10
VOUT to GND -0.3 V Max is VDD + 0.3 V; TA = 25°C 10
VREFIN/VREFOUT to GND -0.3 V Max is VDD + 0.3 V; TA = 25°C 10
Operating Temperature Range (Industrial) -40 105 °C 10
Storage Temperature Range -65 150 °C 10
Junction Temperature TJ MAX 150 °C 10
Reflow Soldering Peak Temperature (Pb Free) 260 °C Pb Free 10
Thermal Impedance θJA 150.4 °C/W TSSOP package 10
Zero-Code Error Drift 2 μV/°C 3
Gain Temperature Coefficient 2.5 ppm Of FSR/°C 3
DC Power Supply Rejection Ratio -80 dB VDD ± 10% 3
DC Output Impedance 0.5 Ω 3
Short-Circuit Current 30 mA VDD = 5 V 3
Power-Up Time 4 μs Coming out of power-down mode VDD = 5 V 3
Reference Input Impedance 14.6 kΩ Per DAC channel 3
Reference Output Impedance 7.5 kΩ 3
High Impedance Leakage Current 0.25 μA 4

CAD (KiCad official)

  • Symbol: AD5666ARUZ-2REEL7
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ad5666aruz-2reel7-etched.step / ad5666aruz-2reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5666aruz-2reel7.step / ad5666aruz-2reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 42ddb93a8b652c8c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF