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AD5665RBRUZ-2

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Analog Devices Digital To Analog Converters (DACs), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5665rbruz-2factory-2.0.0extractor-text

Verified AD5665RBRUZ-2

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5665RBRUZ-2 · TSSOP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 35-page datasheet
  • ✓distributor: lcsc C649994, digikey 505-AD5665RBRUZ-2-ND, mouser 584-AD5665RBRUZ-2
  • ✓family: TSSOP-14_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-oecx2zvi/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.33)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5665rbruz-2.kicad_sym✓ ad5665rbruz-2.kicad_mod✓ ad5665rbruz-2.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 3d ago
viewers ad5665rbruz-2: viewers · Ray 3d ago
ad5665rbruz-2-etched.glb Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2-etched.step ad5665rbruz-2: factory component page (tier=mfr) · Ray 3d ago
ad5665rbruz-2-hero.glb ad5665rbruz-2: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
ad5665rbruz-2-hero.overlay.json Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2.glb Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2.kicad_mod Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2.kicad_sym Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2.lbr Publish 0.1.0 · Ray 3d ago
ad5665rbruz-2.step Publish 0.1.0 · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 3d ago

AD5665RBRUZ-2

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-14

AD5665RBRUZ-2 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDAC input Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, and it can alternatively be tied permanently low.
2 ADDR1 input Three-state address input that sets the two least significant bits (A1, A0) of the 7-bit slave address, as set by the Table 10 pin settings.
3 VDD power_in Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 VOUTA output Analog output voltage from DAC A with rail-to-rail output amplifier operation.
5 VOUTC output Analog output voltage from DAC C with rail-to-rail output amplifier operation.
6 POR input Power-on reset pin where tying it to GND powers up the device to 0 V and tying it to VDD powers up the device to midscale.
7 VREFIN/VREFOUT bidirectional Common reference pin that is the reference output when the internal reference is used and the reference input when an external reference is used, with the default being reference input; the internal reference is only available on R suffix versions.
8 ADDR2 input Three-state address input that sets bits A3 and A2 of the 7-bit slave address, as set by the Table 10 pin settings.
9 CLR input Asynchronous, falling-edge-sensitive clear input that loads zero scale to all input and DAC registers, clearing the outputs to 0 V, and aborts a write if activated during a write sequence.
10 VOUTD output Analog output voltage from DAC D with rail-to-rail output amplifier operation.
11 VOUTB output Analog output voltage from DAC B with rail-to-rail output amplifier operation.
12 GND power_in Ground reference point for all circuitry on the device.
13 SDA bidirectional Bidirectional open-drain serial data line used with SCL to clock data into or out of the 16-bit input register, which should be pulled to the supply with an external pull-up resistor.
14 SCL input Serial clock line used with SDA to clock data into or out of the 16-bit input register.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category ADC/DAC/Data Conversion
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy -16 16 LSB Reduced code range Code 512 to Code 65,024; output unloaded 3
Differential Nonlinearity -1 1 LSB Guaranteed monotonic by design 3
Zero-Code Error 2 10 mV All 0s loaded to DAC register 3
Offset Error -10 10 mV 3
Full-Scale Error -0.5 -0.1 0.5 % FSR All 1s loaded to DAC register 3
Gain Error -1 1 % FSR 3
Zero-Code Error Drift -2 2 µV/°C 3
Gain Temperature Coefficient -2.5 2.5 ppm Of FSR/°C 3
Output Voltage Range 0 V Upper limit VDD; internal reference disabled 3
Capacitive Load Stability 2 nF RL = ∞ 3
Capacitive Load Stability 10 nF RL = 2 kΩ 3
Reference Current 210 260 µA VREF = VDD = 5.5 V 3
Output Voltage (2.5 V reference) 2.495 2.505 V At ambient; VDD = 4.5 V to 5.5 V 4
Reference TC (2.5 V reference) -10 10 ppm/°C 4
Input Current (ADDRx, CLR, LDAC, POR) IIN -1 1 µA 4
Input Current (SDA, SCL) IIN -1 1 µA 4
Output Low Voltage (SDA) VOL 0.4 V ISINK = 3 mA 4
Output Low Voltage (SDA) VOL 0.6 V ISINK = 6 mA 4
Floating-State Leakage Current -1 1 µA 4
Supply Voltage VDD 2.7 5.5 V 4
IDD (Normal Mode) IDD 1 1.16 mA VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V; internal reference off 4
IDD (Normal Mode) IDD 0.9 1.05 mA VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V; internal reference off 4
IDD (Normal Mode) IDD 1.9 2.14 mA VIH = VDD, VIL = GND, full-scale loaded; VDD = 4.5 V to 5.5 V; internal reference on 4
IDD (Normal Mode) IDD 1.4 1.59 mA VIH = VDD, VIL = GND, full-scale loaded; VDD = 2.7 V to 3.6 V; internal reference on 4
IDD (All Power-Down Modes) IDD 0.48 1 µA VIH = VDD, VIL = GND (TSSOP); VDD = 3.6 V to 5.5 V 4
Operating Temperature Range, Industrial -40 105 °C 10
VDD to GND VDD -0.3 7 V 10
VOUT to GND VOUT -0.3 V Upper limit VDD + 0.3 V 10
VREFIN/VREFOUT to GND VREFIN/VREFOUT -0.3 V Upper limit VDD + 0.3 V 10
Digital Input Voltage to GND -0.3 V Upper limit VDD + 0.3 V 10
Storage Temperature Range -65 150 °C 10
Junction Temperature (TJ maximum) TJ 150 °C 10
θJA Thermal Impedance, TSSOP θJA 150.4 °C/W 10
Output Voltage Settling Time 4 7 µs AD5665R/AD5665; ¼ to ¾ scale settling to ±2 LSB 7
Serial clock frequency (high speed mode) fSCL 3.4 MHz High speed mode, CB = 100 pF 8
Serial clock frequency (high speed mode) fSCL 1.7 MHz High speed mode, CB = 400 pF 8
tHIGH, SCL high time t1 60 ns High speed mode, CB = 100 pF 8
tHIGH, SCL high time t1 120 ns High speed mode, CB = 400 pF 8
tLOW, SCL low time t2 160 ns High speed mode, CB = 100 pF 8
tLOW, SCL low time t2 320 ns High speed mode, CB = 400 pF 8
tSU;DAT, data setup time t3 10 ns High speed mode 8
tHD;DAT, data hold time t4 0 70 ns High speed mode, CB = 100 pF 8
tHD;DAT, data hold time t4 0 150 ns High speed mode, CB = 400 pF 8
tSU;STA, repeated start setup time t5 160 ns High speed mode 8
tHD;STA, repeated start hold time t6 160 ns High speed mode 8
tRDA, rise time of SDA signal t9 10 80 ns High speed mode, CB = 100 pF 8
tRDA, rise time of SDA signal t9 20 160 ns High speed mode, CB = 400 pF 8
tFDA, fall time of SDA signal t10 10 80 ns High speed mode, CB = 100 pF 8
tFDA, fall time of SDA signal t10 20 160 ns High speed mode, CB = 400 pF 8
tRCL, rise time of SCL signal t11 10 40 ns High speed mode, CB = 100 pF 8
tRCL, rise time of SCL signal t11 20 80 ns High speed mode, CB = 400 pF 8
tFCL, fall time of SCL signal t12 10 40 ns High speed mode, CB = 100 pF 9
tFCL, fall time of SCL signal t12 20 80 ns High speed mode, CB = 400 pF 9
Pulse width of spike suppressed tSP 0 10 ns High speed mode 9
LDAC pulse width low t13 10 ns High speed mode 9
CLR pulse width low t15 20 ns High speed mode 9

CAD (KiCad official)

  • Symbol: AD5665RBRUZ-2
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: ad5665rbruz-2-etched.step / ad5665rbruz-2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5665rbruz-2.step / ad5665rbruz-2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (35 pp, sha256 92ae60d05500e362, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF