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AD5662ARJZ-2REEL7

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Analog Devices Digital To Analog Converters (DACs), SOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad5662arjz-2reel7factory-2.0.0extractor-text

Verified AD5662ARJZ-2REEL7

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD5662ARJZ-2REEL7 · SOT-23-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C578252, digikey AD5662ARJZ-2REEL7TR-ND, mouser 584-AD5662ARJZ-2R7
  • ✓family: SOT-23-8
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-uypfbtsp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.21)
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad5662arjz-2reel7.kicad_sym✓ ad5662arjz-2reel7.kicad_mod✓ ad5662arjz-2reel7.step
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Ray Publish 0.1.0 f320748 3d ago

AD5662ARJZ-2REEL7

Analog Devices · Digital To Analog Converters (DACs) · SOT-23-8

AD5662ARJZ-2REEL7 from Analog Devices, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled to GND.
2 VREF power_in Reference voltage input that sets the DAC output range, with a reference input range of 0.75 V to VDD.
3 VFB input Feedback connection for the output amplifier, which should be connected to VOUT for normal operation.
4 VOUT output Analog output voltage from the DAC, driven by a rail-to-rail output amplifier.
5 SYNC input Level-triggered active-low frame synchronization input; the DAC updates after the 24th clock unless SYNC is taken high first, which aborts the write.
6 SCLK input Serial clock input; data is clocked into the input shift register on its falling edge at rates up to 30 MHz.
7 DIN input Serial data input to the 24-bit shift register, clocked in on the falling edge of SCLK.
8 GND power_in Ground reference point for all circuitry on the part.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOT-23-8
Category ADC/DAC/Data Conversion
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) -32 8 32 LSB See Figure 4 3
Differential Nonlinearity DNL -1 1 LSB Guaranteed monotonic by design; See Figure 5 3
Zero Code Error 2 10 mV All 0s loaded to DAC register 3
Full-Scale Error -1 -0.2 % FSR All 1s loaded to DAC register 3
Offset Error -10 10 mV 3
Gain Error -1.5 1.5 % FSR 3
Zero Code Error Drift -2 2 μV/°C Guaranteed by design and characterization; not production tested 3
Gain Temperature Coefficient -2.5 2.5 ppm of FSR/°C Guaranteed by design and characterization; not production tested 3
Output Voltage Range VOUT 0 V Upper limit printed as VDD 3
Output Voltage Settling Time 8 10 μs ¼ to ¾ scale change settling to ±2 LSB; RL = 2 kΩ; 0 pF < CL < 200 pF 3
Capacitive Load Stability CL 2 nF RL = ∞ 3
Capacitive Load Stability CL 10 nF RL = 2 kΩ 3
Input Current IIN -2 2 μA All digital inputs 3
Input Low Voltage VINL 0.8 V VDD = 5 V, 3 V 3
Input High Voltage VINH 2 V VDD = 5 V, 3 V 3
Power Supply Voltage VDD 2.7 5.5 V All digital inputs at 0 V or VDD 4
Normal Mode Supply Current IDD 150 250 μA VDD = 4.5 V to 5.5 V; DAC active and excluding load current; VIH = VDD and VIL = GND 4
Normal Mode Supply Current IDD 140 225 μA VDD = 2.7 V to 3.6 V; DAC active and excluding load current; VIH = VDD and VIL = GND 4
Power-Down Mode Supply Current IDD 0.48 1 μA All power-down modes; VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND 4
Power-Down Mode Supply Current IDD 0.1 0.375 μA All power-down modes; VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND 4
Reference Current IREF 40 75 μA VREF = VDD = 5 V 3
Reference Current IREF 30 50 μA VREF = VDD = 3.6 V 3
VDD to GND VDD -0.3 7 V TA = 25°C 6
VOUT to GND VOUT -0.3 V Upper limit printed as VDD + 0.3 V 6
Operating Temperature Range (Y Version) TA -40 125 °C 6
Storage Temperature Range TSTG -65 150 °C 6
Junction Temperature TJ 150 °C TJ max 6
Thermal Impedance, Junction-to-Ambient θJA 119 °C/W SOT-23 package, 4-layer board 6
Timing t1: SCLK cycle time t1 50 ns VDD = 2.7 V to 3.6 V; max SCLK 20 MHz at this range 5
Timing t1: SCLK cycle time t1 33 ns VDD = 3.6 V to 5.5 V; max SCLK 30 MHz at this range 5
Timing t2: SCLK high time t2 13 ns VDD = 2.7 V to 5.5 V 5
Timing t3: SCLK low time t3 13 ns VDD = 2.7 V to 5.5 V 5
Timing t4: SYNC to SCLK falling edge setup time t4 13 ns VDD = 2.7 V to 5.5 V 5
Timing t5: Data setup time t5 5 ns VDD = 2.7 V to 5.5 V 5
Timing t6: Data hold time t6 4.5 ns VDD = 2.7 V to 5.5 V 5
Timing t7: SCLK falling edge to SYNC rising edge t7 0 ns VDD = 2.7 V to 5.5 V 5
Timing t8: Minimum SYNC high time t8 50 ns VDD = 2.7 V to 3.6 V 5
Timing t8: Minimum SYNC high time t8 33 ns VDD = 3.6 V to 5.5 V 5
Timing t9: SYNC rising edge to SCLK fall ignore t9 13 ns VDD = 2.7 V to 5.5 V 5
Timing t10: SCLK falling edge to SYNC fall ignore t10 0 ns VDD = 2.7 V to 5.5 V 5
Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz 3
Output Noise (0.1 Hz to 10 Hz) 10 μV p-p DAC code = midscale 3
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB change around major carry 3
Short-Circuit Current 30 mA VDD = 5 V, 3 V 3
Power-Up Time 4 μs Coming out of power-down mode; VDD = 5 V, 3 V 3
Slew Rate 1.5 V/μs ¼ to ¾ scale 3

CAD (KiCad official)

  • Symbol: AD5662ARJZ-2REEL7
  • Footprint: Package_TO_SOT_SMD:SOT-23-8
  • 3D model: SOT-23-8 (KiCad packages3D, STEP)
  • 3D model files: ad5662arjz-2reel7-etched.step / ad5662arjz-2reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5662arjz-2reel7.step / ad5662arjz-2reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 3f3377bce3423dc9, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF