AD5660ARJZ-3500RL7 from Analog Devices, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply input; these parts can operate from 2.7 V to 5.5 V and VDD should be decoupled to GND.
2	VREFOUT	output	Reference voltage output; the internal reference for this part (2.5 V for the AD5660ARJZ-3500RL7 per the ordering guide) is available at this pin.
3	VFB	input	Feedback connection for the output amplifier, which should be connected to VOUT for normal operation.
4	VOUT	output	Analog output voltage from the DAC, with rail-to-rail operation of the output amplifier.
5	SYNC	input	Level-triggered active-low frame synchronization input; the DAC updates after the 24th clock cycle for the AD5660 unless SYNC is taken high first, in which case the write is ignored.
6	SCLK	input	Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz.
7	DIN	input	Serial data input; the AD5660 has a 24-bit shift register, and data is clocked in on the falling edge of SCLK.
8	GND	power_in	Ground reference point for all circuitry on the part.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOT-23-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Resolution (AD5660)		16			Bits	A grade	3
Relative Accuracy (AD5660)		-32		32	LSB	A grade, printed as ±32 LSB max	3
Differential Nonlinearity (AD5660)		-1		1	LSB	A grade, guaranteed monotonic by design	3
Output Voltage Range		0			V	A grade; max printed as VDD	3
Output Voltage Settling Time				10	µs	¼ to ¾ scale change settling to ±2 LSB; RL = 2 kΩ; 0 pF < CL < 200 pF	3
SCLK cycle time	t1	50			ns	VDD = 2.7 V to 3.6 V	7
SCLK cycle time	t1	33			ns	VDD = 3.6 V to 5.5 V	7
SCLK high time	t2	13			ns	VDD = 2.7 V to 3.6 V	7
SCLK low time	t3	13			ns	VDD = 2.7 V to 3.6 V	7
SYNC to SCLK falling edge setup time	t4	13			ns	VDD = 2.7 V to 3.6 V	7
Data setup time	t5	5			ns	VDD = 2.7 V to 3.6 V	7
Data hold time	t6	4.5			ns	VDD = 2.7 V to 3.6 V	7
SCLK falling edge to SYNC rising edge	t7	0			ns	VDD = 2.7 V to 3.6 V	7
Minimum SYNC high time	t8	50			ns	VDD = 2.7 V to 3.6 V	7
Minimum SYNC high time	t8	33			ns	VDD = 3.6 V to 5.5 V	7
SYNC rising edge to SCLK fall ignore	t9	13			ns	VDD = 2.7 V to 3.6 V	7
SCLK falling edge to SYNC fall ignore	t10	0			ns	VDD = 2.7 V to 3.6 V	7
Maximum SCLK frequency				20	MHz	VDD = 2.7 V to 3.6 V	7
Maximum SCLK frequency				30	MHz	VDD = 3.6 V to 5.5 V	7
VDD to GND	VDD	-0.3		7	V		8
VOUT to GND	VOUT	-0.3			V	Upper limit printed as VDD + 0.3 V	8
VFB to GND	VFB	-0.3			V	Upper limit printed as VDD + 0.3 V	8
VREFOUT to GND	VREFOUT	-0.3			V	Upper limit printed as VDD + 0.3 V	8
Digital Input Voltage to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	8
Operating Temperature Range (Industrial)		-40		105	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature	TJ max			150	°C		8
Reflow Soldering Peak Temperature (SnPb)				240	°C		8
Reflow Soldering Peak Temperature (Pb-Free)				260	°C		8
Supply voltage (VDD) operating range	VDD	2.7		5.5	V	Pin 1 VDD; decouple to GND	9
Thermal Impedance, junction-to-ambient	θJA		119		°C/W	SOT-23 package, 4-layer board	8

CAD (KiCad official)

Symbol: AD5660ARJZ-3500RL7
Footprint: Package_TO_SOT_SMD:SOT-23-8
3D model: SOT-23-8 (KiCad packages3D, STEP)
3D model files: ad5660arjz-3500rl7-etched.step / ad5660arjz-3500rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5660arjz-3500rl7.step / ad5660arjz-3500rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 f2131f1417ffb106, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5660ARJZ-3500RL7

Verified AD5660ARJZ-3500RL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README