# AD5641BKSZ-REEL7

**Analog Devices** · Digital To Analog Converters (DACs) · SC-70-6

AD5641BKSZ-REEL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SYNC | input | Level-triggered active-low frame synchronization input; when low it enables the input shift register, the DAC updates after the 16th clock unless SYNC is taken high first, and the rising edge then acts as an interrupt that causes the write sequence to be ignored. |
| 2 | SCLK | input | Serial clock input that clocks data into the input shift register on its falling edge, at rates up to 30 MHz. |
| 3 | SDIN | input | Serial data input to a 16-bit shift register, with data clocked in on the falling edge of the serial clock. |
| 4 | VDD | power_in | Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled to GND. |
| 5 | GND | power_in | Ground reference point for all circuitry on the AD5641. |
| 6 | VOUT | output | Analog DAC output voltage from the output amplifier, which has rail-to-rail operation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | ADC/DAC/Data Conversion |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (INL) | INL | -4 |  | 4 | LSB | B grade; linearity over code 256 to 16,128 (footnote 1) | 3 |
| Differential Nonlinearity | DNL | -1 |  | 1 | LSB | Guaranteed monotonic by design | 3 |
| Zero-Code Error |  |  | 0.5 | 10 | mV | All 0s loaded to DAC register | 3 |
| Offset Error |  | -10 | 0.63 | 10 | mV |  | 3 |
| Full-Scale Error |  | -0.5 |  | 0.5 | mV | All 1s loaded to DAC register | 3 |
| Gain Error |  | -0.037 | 0.004 | 0.037 | % of FSR |  | 3 |
| Output Voltage Range | VOUT | 0 |  |  | V | Upper limit printed as VDD | 3 |
| Output Voltage Settling Time |  |  | 6 | 10 | µs | Code ¼ scale to ¾ scale, to ±1 LSB | 3 |
| Input Current | IIN | -2 |  | 2 | µA |  | 3 |
| Input Low Voltage | VINL |  |  | 0.8 | V | VDD = 4.5 V to 5.5 V | 3 |
| Input Low Voltage | VINL |  |  | 0.6 | V | VDD = 2.7 V to 3.6 V | 3 |
| Input High Voltage | VINH | 1.8 |  |  | V | VDD = 4.5 V to 5.5 V | 3 |
| Input High Voltage | VINH | 1.4 |  |  | V | VDD = 2.7 V to 3.6 V | 3 |
| Supply Voltage | VDD | 2.7 |  | 5.5 | V | All digital inputs at 0 V or VDD | 3 |
| IDD (Normal Mode) | IDD |  | 75 | 100 | µA | VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND; excluding load current | 3 |
| IDD (Normal Mode) | IDD |  | 60 | 90 | µA | VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; excluding load current | 3 |
| SCLK cycle time | t1 | 33 |  |  | ns |  | 4 |
| SCLK high time | t2 | 5 |  |  | ns |  | 4 |
| SCLK low time | t3 | 5 |  |  | ns |  | 4 |
| SYNC to SCLK falling edge setup time | t4 | 10 |  |  | ns |  | 4 |
| Data setup time | t5 | 5 |  |  | ns |  | 4 |
| Data hold time | t6 | 4.5 |  |  | ns |  | 4 |
| SCLK falling edge to SYNC rising edge | t7 | 0 |  |  | ns |  | 4 |
| Minimum SYNC high time | t8 | 20 |  |  | ns |  | 4 |
| SYNC rising edge to next SCLK falling edge ignored | t9 | 13 |  |  | ns |  | 4 |
| VDD to GND | VDD | -0.3 |  | 7 | V | TA = 25°C | 5 |
| Digital Input Voltage to GND |  | -0.3 |  |  | V | Upper limit printed as VDD + 0.3 V | 5 |
| VOUT to GND | VOUT | -0.3 |  |  | V | Upper limit printed as VDD + 0.3 V | 5 |
| Operating Temperature Range (Industrial) | TA | -40 |  | 125 | °C | Industrial | 5 |
| Storage Temperature Range | TSTG | -65 |  | 160 | °C |  | 5 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 5 |
| ESD |  |  |  | 2 | kV |  | 5 |
| Reflow Soldering Peak Temperature |  |  |  | 260 | °C | Reflow soldering | 5 |
| Time at Reflow Peak Temperature |  | 20 |  | 40 | sec | Reflow soldering | 5 |
| Thermal Impedance, Junction-to-Ambient (SC70) | θJA |  | 433.34 |  | °C/W | SC70 package | 5 |
| Thermal Impedance, Junction-to-Case (SC70) | θJC |  | 149.47 |  | °C/W | SC70 package | 5 |

## CAD (KiCad official)

- Symbol: `AD5641BKSZ-REEL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad5641bksz-reel7-etched.step` / `ad5641bksz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5641bksz-reel7.step` / `ad5641bksz-reel7.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD5641.pdf) (20 pp, sha256 `1fb231a400082c61`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad5641bksz-reel7-datasheet.pdf)