component
AD5640BRJZ-1500RL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), SOT-23-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD5640BRJZ-1500RL7
Analog Devices · Digital To Analog Converters (DACs) · SOT-23-8
AD5640BRJZ-1500RL7 from Analog Devices, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input; these parts can operate from 2.7 V to 5.5 V and VDD should be decoupled to GND. |
| 2 | VREFOUT | output | Reference voltage output that provides the internal reference (1.25 V or 2.5 V depending on the variant). |
| 3 | VFB | input | Feedback connection for the output amplifier, which should be connected to VOUT for normal operation. |
| 4 | VOUT | output | Analog output voltage from the DAC, with the output amplifier providing rail-to-rail operation. |
| 5 | SYNC | input | Level-triggered active-low frame synchronization input; the DAC updates after the 16th falling SCLK edge for the AD5640 unless SYNC is taken high first, in which case the rising edge acts as an interrupt and the write is ignored. |
| 6 | SCLK | input | Serial clock input; data is clocked into the input shift register on the falling edge, at rates up to 30 MHz. |
| 7 | DIN | input | Serial data input; the AD5640 has a 16-bit shift register and data is clocked in on the falling edge of SCLK. |
| 8 | GND | power_in | Ground reference point for all circuitry on the part. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOT-23-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C, unless otherwise noted | 8 | |
| VOUT to GND (max printed as VDD + 0.3 V) | VOUT | -0.3 | V | TA = 25°C, unless otherwise noted | 8 | ||
| VFB to GND (max printed as VDD + 0.3 V) | VFB | -0.3 | V | TA = 25°C, unless otherwise noted | 8 | ||
| VREFOUT to GND (max printed as VDD + 0.3 V) | VREFOUT | -0.3 | V | TA = 25°C, unless otherwise noted | 8 | ||
| Digital Input Voltage to GND (max printed as VDD + 0.3 V) | -0.3 | V | TA = 25°C, unless otherwise noted | 8 | |||
| Operating Temperature Range (Industrial) | -40 | 105 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature (TJ max) | TJ | 150 | °C | 8 | |||
| Reflow Soldering Peak Temperature | 240 | °C | SnPb | 8 | |||
| Reflow Soldering Peak Temperature | 260 | °C | Pb-Free | 8 | |||
| Power Supply Input Voltage (VDD) | VDD | 2.7 | 5.5 | V | Pin 1 description: these parts can operate from 2.7 V to 5.5 V | 9 | |
| SCLK cycle time (t1) | t1 | 50 | ns | VDD = 2.7 V to 3.6 V; SCLK cycle time | 7 | ||
| SCLK cycle time (t1) | t1 | 33 | ns | VDD = 3.6 V to 5.5 V; SCLK cycle time | 7 | ||
| SCLK high time (t2) | t2 | 13 | ns | VDD = 2.7 V to 3.6 V; SCLK high time | 7 | ||
| SCLK low time (t3) | t3 | 13 | ns | VDD = 2.7 V to 3.6 V; SCLK low time | 7 | ||
| SYNC to SCLK falling edge setup time (t4) | t4 | 13 | ns | VDD = 2.7 V to 3.6 V; SYNC to SCLK falling edge setup time | 7 | ||
| Data setup time (t5) | t5 | 5 | ns | VDD = 2.7 V to 3.6 V; Data setup time | 7 | ||
| Data hold time (t6) | t6 | 4.5 | ns | VDD = 2.7 V to 3.6 V; Data hold time | 7 | ||
| SCLK falling edge to SYNC rising edge (t7) | t7 | 0 | ns | VDD = 2.7 V to 3.6 V; SCLK falling edge to SYNC rising edge | 7 | ||
| Minimum SYNC high time (t8) | t8 | 50 | ns | VDD = 2.7 V to 3.6 V; Minimum SYNC high time | 7 | ||
| Minimum SYNC high time (t8) | t8 | 33 | ns | VDD = 3.6 V to 5.5 V; Minimum SYNC high time | 7 | ||
| SYNC rising edge to SCLK fall ignore (t9) | t9 | 13 | ns | VDD = 2.7 V to 3.6 V; SYNC rising edge to SCLK fall ignore | 7 | ||
| SCLK falling edge to SYNC fall ignore (t10) | t10 | 0 | ns | VDD = 2.7 V to 3.6 V; SCLK falling edge to SYNC fall ignore | 7 | ||
| Maximum SCLK frequency | 20 | MHz | VDD = 2.7 V to 3.6 V (footnote 1 to Table 4) | 7 | |||
| Maximum SCLK frequency | 30 | MHz | VDD = 3.6 V to 5.5 V (footnote 1 to Table 4) | 7 | |||
| Thermal Impedance, SOT-23 package | θJA | 119 | °C/W | 4-Layer Board | 8 |
CAD (KiCad official)
- Symbol:
AD5640BRJZ-1500RL7 - Footprint:
Package_TO_SOT_SMD:SOT-23-8 - 3D model: SOT-23-8 (KiCad packages3D, STEP)
- 3D model files:
ad5640brjz-1500rl7-etched.step/ad5640brjz-1500rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad5640brjz-1500rl7.step/ad5640brjz-1500rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
f2131f1417ffb106, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).