AD5629RARUZ-1 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LDAC	input	Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data, or the pin can be tied permanently low.
2	A0	input	Address input that sets the least significant bit of the 7-bit slave address.
3	VDD	power_in	Power supply input that operates from 2.7 V to 5.5 V and should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4	VOUTA	output	Analog output voltage from DAC A, with a rail-to-rail output amplifier.
5	VOUTC	output	Analog output voltage from DAC C, with a rail-to-rail output amplifier.
6	VOUTE	output	Analog output voltage from DAC E, with a rail-to-rail output amplifier.
7	VOUTG	output	Analog output voltage from DAC G, with a rail-to-rail output amplifier.
8	VREFIN/VREFOUT	bidirectional	Common reference pin that acts as the reference output when the internal reference is used and as the reference input when an external reference is used, defaulting to reference input.
9	CLR	input	Falling-edge-sensitive asynchronous clear input that ignores all LDAC pulses while low and loads zero scale, midscale or full scale from the CLR code register, defaulting to clearing the output to 0 V.
10	VOUTH	output	Analog output voltage from DAC H, with a rail-to-rail output amplifier.
11	VOUTF	output	Analog output voltage from DAC F, with a rail-to-rail output amplifier.
12	VOUTD	output	Analog output voltage from DAC D, with a rail-to-rail output amplifier.
13	VOUTB	output	Analog output voltage from DAC B, with a rail-to-rail output amplifier.
14	GND	power_in	Ground reference point for all circuitry on the part.
15	SDA	bidirectional	Bidirectional open-drain serial data line that clocks data into or out of the 32-bit input shift register and must be pulled to the supply with an external pull-up resistor.
16	SCL	input	Serial clock line used with SDA to clock data into or out of the 32-bit input shift register.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	ADC/DAC/Data Conversion
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (AD5629R)		-4	0.5	4	LSB	See Figure 7	3
Differential Nonlinearity (AD5629R)		-0.25		0.25	LSB	Guaranteed monotonic by design (see Figure 9)	3
Zero-Code Error			6	19	mV	All 0s loaded to DAC register (see Figure 19)	3
Zero-Code Error Drift		-2		2	µV/°C		3
Full-Scale Error			-0.2	-1	% FSR	All 1s loaded to DAC register (see Figure 20)	3
Gain Error		-1		1	% FSR		3
Gain Temperature Coefficient		-2.5		2.5	ppm Of FSR/°C		3
Offset Error		-19	6	19	mV		3
Output Voltage Range		0			V	Upper limit printed as VDD	3
Reference Input Range		0			V	Upper limit printed as VDD	3
Reference Current			40	50	µA	VREFIN = VDD = 5.5 V (per DAC channel)	3
Input Current		-3		3	µA	All digital inputs	4
Input Low Voltage	VINL			0.8	V	VDD = 5 V	4
Input High Voltage	VINH	2			V	VDD = 5 V	4
Reference Tempco		-15	5	15	ppm/°C	LFCSP, TSSOP	5
Reference Output Voltage (1.25 V option)		1.247		1.253	V	TA = 25°C	5
Supply Voltage (1.25 V reference option)	VDD	2.7		5.5	V	Devices with 1.25 V reference selected	1
Supply Voltage	VDD	2.7		3.6	V	All digital inputs at 0 or VDD, DAC active, excludes load current	6
IDD (Normal Mode), internal reference off	IDD		1	1.5	mA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND	6
IDD (Normal Mode), internal reference on	IDD		1.8	2.25	mA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND; internal reference on	6
IDD (All Power-Down Modes)	IDD		0.2	1	µA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND	6
Output Voltage Settling Time			2.5	7	µs	¼ to ¾ scale settling to ±2 LSB	6
VDD to GND (absolute maximum)	VDD	-0.3		7	V		9
Digital Input Voltage to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	9
VOUT to GND	VOUT	-0.3			V	Upper limit printed as VDD + 0.3 V	9
VREFIN/VREFOUT to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	9
Operating Temperature Range		-40		105	°C	Industrial	9
Storage Temperature Range		-65		150	°C		9
Junction Temperature	TJ MAX			150	°C		9
Reflow Soldering Peak Temperature				260	°C	Pb free	9
Serial clock frequency (standard mode)	fSCL			100	kHz	Standard mode	7
Serial clock frequency (fast mode)	fSCL			400	kHz	Fast mode	7
DC Power Supply Rejection Ratio			-80		dB	VDD ± 10%	3
DC Crosstalk (External Reference), full-scale output change			10		µV	Due to full-scale output change, RL = 2 kΩ to GND or VDD	3
DC Crosstalk (External Reference), load current change			5		µV/mA	Due to load current change	3
DC Crosstalk (External Reference), powering down			10		µV	Due to powering down (per channel)	3
DC Crosstalk (Internal Reference), full-scale output change			25		µV	Due to full-scale output change, RL = 2 kΩ to GND or VDD	3
DC Crosstalk (Internal Reference), load current change			10		µV/mA	Due to load current change	3
Capacitive Load Stability			2		nF	RL = ∞	3
Capacitive Load Stability			10		nF	RL = 2 kΩ	3
DC Output Impedance			0.5		Ω		3
Short-Circuit Current			30		mA	VDD = 5 V	3
Power-Up Time			4		µs	Coming out of power-down mode, VDD = 5 V	3
Reference Input Impedance			14.6		kΩ		3
Reference Output Impedance			7.5		kΩ		5
Pin Capacitance			3		pF		4
Output Voltage Slew Rate			1.2		V/µs		6
Digital-to-Analog Glitch Impulse			4		nV-s	1 LSB change around major carry (see Figure 35)	6
Digital Feedthrough			0.1		nV-s		6
Reference Feedthrough			-90		dB	VREFIN = 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz	6
Digital Crosstalk			0.2		nV-s		6
Analog Crosstalk			0.4		nV-s		6
DAC-to-DAC Crosstalk			0.8		nV-s		6
Multiplying Bandwidth			320		kHz	VREFIN = 2 V ± 0.2 V p-p	6
Total Harmonic Distortion			-80		dB	VREFIN = 2 V ± 0.1 V p-p, frequency = 10 kHz	6
Output Noise Spectral Density			120		nV/√Hz	DAC code = 0x8400, 1 kHz	6
Output Noise Spectral Density			100		nV/√Hz	DAC code = 0x8400, 10 kHz	6
Thermal Impedance, junction to ambient (16-Lead TSSOP, 4-Layer Board)	θJA		112.6		°C/W	16-Lead TSSOP (4-Layer Board)	9

CAD (KiCad official)

Symbol: AD5629RARUZ-1
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad5629raruz-1-etched.step / ad5629raruz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5629raruz-1.step / ad5629raruz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (30 pp, sha256 37f9592e835fdce3, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5629RARUZ-1

Verified AD5629RARUZ-1

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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